公开(公告)号：US20100308417A1

公开(公告)日：2010-12-09

申请号：US12858797

申请日：2010-08-18

Applicant: Takahiro YOKOYAMA

Inventor： Takahiro YOKOYAMA

IPC: H01L27/088

CPC classification number: G11C11/4125 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  Y10S257/903 ,  Y10S257/904

Abstract: In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer in the word line direction than in the bit line direction) including first and second driver MOS transistors, first and second load MOS transistors and first and second access MOS transistors, two capacitors are arranged spaced apart from each other on embedded interconnections to be storage nodes, with lower and upper cell plates cross-coupled to each other.

Abstract translation: 在具有包括第一和第二驱动器MOS晶体管的横向型单元（具有在字线延伸方向上并排布置并且在字线方向上比在位线方向上更长的三个分隔阱的存储单元）的完整CMOS SRAM中， 和第二负载MOS晶体管以及第一和第二存取MOS晶体管，两个电容器在嵌入式互连上彼此间隔布置成为存储节点，下单元板和上单元板彼此交叉耦合。

公开(公告)号：US20100302693A1

公开(公告)日：2010-12-02

申请号：US12783472

申请日：2010-05-19

Applicant: Yutaka HAYASHI

Inventor： Yutaka HAYASHI

IPC: H02H9/00

CPC classification number: H01L27/0251 ,  H01L29/0834 ,  H01L29/0878 ,  H01L29/7393 ,  H01L29/7816 ,  H02H9/046

Abstract: The present invention provides a technique capable of realizing an ESD protection performance having a high ESD withstand voltage in a small layout area. An ESD protection circuit includes a clamping circuit, Zener diodes, a transistor comprised of a DMOS, a transistor comprised of an IGBT, and resistors. The ESD protection circuit effectively protects the protected circuit such that the transistor comprised of the DMOS is caused to absorb the current noise at the time of operating the protected circuit to prevent malfunction due to latchup and the IGBT (the transistor comprised of IGBT) whose current absorption capacity is increased by the thyristor effect is operated in parallel for a large current at the time of ESD.

Abstract translation: 本发明提供一种能够在小布局区域中实现具有高ESD耐受电压的ESD保护性能的技术。 ESD保护电路包括钳位电路，齐纳二极管，由DMOS组成的晶体管，由IGBT构成的晶体管和电阻器。 ESD保护电路有效地保护受保护的电路，使得由DMOS组成的晶体管能够在操作受保护电路时吸收电流噪声，以防止由于闭锁引起的故障和IGBT（IGBT的晶体管） 通过晶闸管效应，在ESD下大电流并联工作时，吸收容量增加。

公开(公告)号：US20100301429A1

公开(公告)日：2010-12-02

申请号：US12728198

申请日：2010-03-20

Applicant: TOSHIHIDE NABATAME

Inventor： TOSHIHIDE NABATAME

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/518

Abstract: In a p-channel-type field-effect transistor having a metal gate electrode, a technique capable of stably obtaining a desired threshold voltage is provided. On a gate insulating film composed of a HfSiON film and formed on a semiconductor substrate, there is formed a metal gate electrode partially having a conductive film with a Me1-xAlxOy (0.2≦x≦0.75, 0.2≦y≦1.5) composition having a Me-O—Al—O-Me bond or a metal gate electrode partially having a conductive film with a Me1-xAlxN1-zOz (0.2≦x≦0.75, 0.1≦z≦0.9) composition having a Me-O—Al—N-Me bond.

Abstract translation: 在具有金属栅电极的p沟道型场效应晶体管中，提供了能够稳定地获得期望阈值电压的技术。 在由半导体衬底上形成的由HfSiON膜构成的栅极绝缘膜上，形成部分地具有导电膜的金属栅电极，该导电膜具有Me1-xAlxOy（0.2＆amp; NlE; x＆amp; nlE; 0.75,0.2＆nlE; y＆nlE; 1.5）组成 具有Me-O-Al-O-Me键或部分具有导电膜的金属栅极电极，其具有Me1-xAlxN1-zOz（0.2＆amp; NlE; x＆amp; nlE; 0.75,0.1＆ -Al-N-Me键。

公开(公告)号：US20100297960A1

公开(公告)日：2010-11-25

申请号：US12805409

申请日：2010-07-29

Applicant: Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

Inventor： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

IPC: H04B1/44 ,  H01L29/778

CPC classification number: H01L27/0605 ,  H01L27/0629 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7783 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A switching element is provided that realizes an stabilize a potential between the gates of the multi-gates without an increase in the insertion loss, and an antenna switch circuit and a radio frequency module each using the switch element. The switching element includes two ohmic electrodes 39, 40 formed on a semiconductor substrate, at least two gate electrodes 41, 42 disposed between the two ohmic electrodes, and a conductive region 45 disposed between the adjacent gate electrodes among the at least two gate electrodes, a field effective transistor being structured by the two ohmic electrodes, the at least two gate electrodes, and the conductive region. The conductive region has a wider portion that is wider in width than the conductive region interposed between the adjacent gate electrodes on one end thereof. The distance between the adjacent gate electrodes is narrower than the width of the wider portion. Resistors 44, 46 are connected in series between the two ohmic electrodes through the wider portion.

公开(公告)号：US20100289127A1

公开(公告)日：2010-11-18

申请号：US12776376

申请日：2010-05-08

Applicant: Takamitsu Kanazawa ,  Toshiyuki Hata

Inventor： Takamitsu Kanazawa ,  Toshiyuki Hata

IPC: H01L23/495

CPC classification number: H01L23/49562 ,  H01L21/4842 ,  H01L23/4006 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85375 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18301 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01026 ,  H01L2224/05552 ,  H01L2924/00015

Abstract: A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Abstract translation: 其中减少了构成功率半导体模块的半导体封装的布线电阻和寄生电感的半导体器件。 在半导体器件中，其上形成有IGBT的半导体芯片和二极管芯片安装在管芯焊盘的上表面上。 半导体芯片的发射极焊盘和二极管芯片的阳极焊盘通过Al线与引线耦合。 引线的一端位于比管芯焊盘的上表面更高的位置，以缩短用于耦合发射极焊盘和引线的Al线的长度。

公开(公告)号：US20100283108A1

公开(公告)日：2010-11-11

申请号：US12765571

申请日：2010-04-22

Applicant: Mahito Sawada ,  Tatsunori Kaneoka ,  Katsuyuki Horita

Inventor： Mahito Sawada ,  Tatsunori Kaneoka ,  Katsuyuki Horita

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3105 ,  H01L21/76205 ,  H01L21/76229 ,  H01L27/088

Abstract: To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.

Abstract translation: 提供一种具有能够阻碍对半导体元件的电特性的不利影响的元件隔离结构的半导体器件及其制造方法。 留在具有相对窄的宽度的浅沟槽隔离中的第一氧化硅膜的厚度比留在具有较宽宽度的浅沟槽隔离中的第一氧化硅膜薄。 通过HDP-CVD法具有相对高的压缩应力的第二氧化硅膜（上层）通过第一氧化硅膜的厚度较薄地层叠在下层的第一氧化硅膜上。 最终形成在具有相对窄的宽度的浅沟槽隔离中的元件隔离氧化膜的压缩应力被更强化。

公开(公告)号：US20100277503A1

公开(公告)日：2010-11-04

申请号：US12835897

申请日：2010-07-14

Applicant: GORO SAKAMAKI ,  Takashi Ohyama ,  Shigeru Ohta ,  Kei Tanabe

Inventor： GORO SAKAMAKI ,  Takashi Ohyama ,  Shigeru Ohta ,  Kei Tanabe

IPC: G09G5/00

CPC classification number: G09G5/363 ,  G09G3/3611 ,  G09G3/3685 ,  G09G5/12 ,  G09G5/393 ,  G09G5/395 ,  G09G2310/027 ,  G09G2320/0247 ,  G09G2320/0261 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2340/125 ,  G09G2360/18

Abstract: No flicker is displayed on the display screen during display of moving pictures and power consumption can be reduced by adding a high quality moving picture display function. Moreover, the number of times of transfer of moving pictures by comprising a still-picture·text·system·I/O bus·interface and a moving picture interface (external display interface), providing a display operation change register (DM) and a RAM access change register (RM) which are changed selectively depending on display content (display mode) displayed on a display device and displaying the display data on the display device via a picture memory even in the moving picture display mode.

Abstract translation: 显示动态图像时，显示屏上不显示闪烁，通过添加高质量的动态图像显示功能可以降低功耗。 此外，通过包括静止图像·文本·系统·I / O总线·接口和运动图像接口（外部显示接口）的移动图像的传送次数，提供显示操作改变寄存器（DM）和 RAM访问改变寄存器（RM），其根据显示在显示装置上的显示内容（显示模式）选择性地改变，并且即使在运动图像显示模式下也经由图像存储器将显示数据显示在显示装置上。

公开(公告)号：US20100270634A1

公开(公告)日：2010-10-28

申请号：US12832505

申请日：2010-07-08

Applicant: Tatsunori MURATA ,  Mikio Tsujiuchi

Inventor： Tatsunori MURATA ,  Mikio Tsujiuchi

IPC: H01L29/82

CPC classification number: H01L27/224 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F41/302 ,  H01F41/307 ,  H01L43/08 ,  H01L43/12

Abstract: The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH3 or H2 as pretreatment. Thereafter, a tensile stress silicon nitride film to impose tensile stress on an MTJ device is formed over a clad layer and over an interlayer dielectric film where the clad layer is not formed. Successively, a compressive stress silicon nitride film to impose compressive stress on the MTJ device is formed over the tensile stress silicon nitride film. The conditions for forming the tensile stress silicon nitride film and the compressive stress silicon nitride film are as follows: a parallel plate type plasma CVD apparatus is used; the RF power is set in the range of 0.03 to 0.4 W/cm2; and the film forming temperature is set in the range of 200° C. to 350° C.

Abstract translation: 本发明使得可以获得：能够形成高可靠性上线的半导体器件，而对MTJ器件的磁性材料的性能没有有害影响; 及其制造方法。 使用可还原NH3或H2作为预处理进行等离子体处理。 此后，在覆层和覆盖层未形成的层间电介质膜上形成在MTJ器件上施加拉伸应力的拉伸应力氮化硅膜。 接着，在拉伸应力氮化硅膜上形成在MTJ装置上施加压应力的压应力氮化硅膜。 用于形成拉伸应力氮化硅膜和压缩应力氮化硅膜的条件如下：使用平行板型等离子体CVD装置; RF功率设定在0.03〜0.4W / cm 2的范围内; 成膜温度设定在200〜350℃的范围。

公开(公告)号：US20100270365A1

公开(公告)日：2010-10-28

申请号：US12831667

申请日：2010-07-07

Applicant: Yoichi KUKIMOTO ,  Kazuki Ikeda ,  Hitoshi Sakurai ,  Nobuhiro Kinoshita ,  Masaki Nakanishi

Inventor： Yoichi KUKIMOTO ,  Kazuki Ikeda ,  Hitoshi Sakurai ,  Nobuhiro Kinoshita ,  Masaki Nakanishi

IPC: B23K1/20

CPC classification number: B23K35/025 ,  B22F1/007 ,  B23K35/36 ,  H01L24/73 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01327 ,  H05K1/111 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/0215 ,  H05K2201/09381 ,  H05K2203/043 ,  Y10T428/12035 ,  Y10T428/12493 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The present invention relates to a solder paste composition used for precoating an electrode surface with solder. A first solder paste composition is contains a solder powder and a flux, and a metallic powder made by metallic species different from metallic species constituting the solder powder and metallic species constituting the electrode surface in a rate of 0.1% by weight or more and 20% by weight or less based on a total amount of the solder powder. When these solder paste compositions are evenly applied onto an electronic circuit substrate for precoating, such a solder that does not generate any swollen portion, solder-lacking portion and variability in a height thereof can be formed irrespective of a shape of a pad.

Abstract translation: 本发明涉及一种用于用焊料预涂电极表面的焊膏组合物。 第一焊膏组合物含有焊料粉末和焊剂，以及由构成焊料粉末的金属物质的金属物质构成的金属粉末和构成电极表面的金属物质的比例为0.1重量％以上且20重量％ 或更少的焊锡粉末。 当将这些焊膏组合物均匀地涂覆到用于预涂层的电子电路基板上时，可以形成不产生任何溶胀部分的焊料，焊料缺乏部分和其高度的变化性，而与焊盘的形状无关。

公开(公告)号：US20100264414A1

公开(公告)日：2010-10-21

申请号：US12761350

申请日：2010-04-15

Applicant: Takuro HOMMA ,  Katsuhiko Hotta ,  Takashi Moriyama

Inventor： Takuro HOMMA ,  Katsuhiko Hotta ,  Takashi Moriyama

IPC: H01L23/544 ,  H01L21/66 ,  H01L23/485 ,  H01L21/768

CPC classification number: H01L23/50 ,  H01L22/32 ,  H01L23/3192 ,  H01L23/4827 ,  H01L24/03 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48624 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In the current manufacturing process of LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by the voltage-application test (high-temperature and high-humidity test) in an environment of high temperature (such as an approximate range from 85 to 130° C.) and high humidity (such as about 80% RH). For that test, the inventors of the present invention found the phenomenon of occurrence of separation of titanium nitride film as the anti-reflection film from upper film and of generation of cracks in the titanium nitride film at an edge part of upper surface of the aluminum-based bonding pad applied with a positive voltage during the high-temperature and high-humidity test caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. An invention of the present application is to remove the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.

Abstract translation: 在目前的LSI或半导体集成电路装置的制造工序中，组装装置（树脂密封工序）的步骤通常在高温环境下进行电压施加试验（高温高湿试验） 温度（例如约85〜130℃的大致范围）和高湿度（例如约80％RH）。 对于该试验，本发明的发明人发现，作为防反射膜从上部膜分离出氮化钛膜的发生现象，并且在铝的上表面的边缘部分产生氮化钛膜中的裂纹 在由于通过密封树脂等的水分引起的电化学反应引起的高温高湿试验期间施加正电压的氧化钛基焊盘产生氮化钛膜的氧化和膨胀。 本申请的发明是在铝基焊盘的周边区域以环或狭缝形状除去焊盘上的氮化钛膜。