公开(公告)号：US07772662B2

公开(公告)日：2010-08-10

申请号：US12424982

申请日：2009-04-16

Applicant: Tatsunori Murata ,  Mikio Tsujiuchi

Inventor： Tatsunori Murata ,  Mikio Tsujiuchi

IPC: H01L29/82

CPC classification number: H01L27/224 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F41/302 ,  H01F41/307 ,  H01L43/08 ,  H01L43/12

Abstract: The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH3 or H2 as pretreatment. Thereafter, a tensile stress silicon nitride film to impose tensile stress on an MTJ device is formed over a clad layer and over an interlayer dielectric film where the clad layer is not formed. Successively, a compressive stress silicon nitride film to impose compressive stress on the MTJ device is formed over the tensile stress silicon nitride film. The conditions for forming the tensile stress silicon nitride film and the compressive stress silicon nitride film are as follows: a parallel plate type plasma CVD apparatus is used; the RF power is set in the range of 0.03 to 0.4 W/cm2; and the film forming temperature is set in the range of 200° C. to 350° C.

Abstract translation: 本发明使得可以获得：能够形成高可靠性的上线而不会对MTJ装置的磁性材料的性质产生有害影响的半导体器件; 及其制造方法。 使用可还原NH3或H2作为预处理进行等离子体处理。 此后，在覆层和覆盖层未形成的层间电介质膜上形成在MTJ器件上施加拉伸应力的拉伸应力氮化硅膜。 接着，在拉伸应力氮化硅膜上形成在MTJ装置上施加压应力的压应力氮化硅膜。 用于形成拉伸应力氮化硅膜和压缩应力氮化硅膜的条件如下：使用平行板型等离子体CVD装置; RF功率设定在0.03〜0.4W / cm 2的范围内; 并且成膜温度设定在200℃至350℃的范围内。

公开(公告)号：US20090269860A1

公开(公告)日：2009-10-29

申请号：US12411665

申请日：2009-03-26

Applicant: Tatsunori MURATA ,  Mikio Tsujiuchi ,  Ryoji Matsuda

Inventor： Tatsunori MURATA ,  Mikio Tsujiuchi ,  Ryoji Matsuda

IPC: H01L43/12

CPC classification number: H01L27/228 ,  G11C11/16

Abstract: To provide a manufacturing method of a semiconductor device capable of forming, as a protective film of an MTJ element, a silicon nitride film having good insulation properties without deteriorating the properties of the MTJ element. The method of the invention includes steps of forming a silicon nitride film over the entire surface including an MTJ element portion (MTJ element and an upper electrode) while using a parallel plate plasma CVD apparatus as a film forming apparatus and a film forming gas not containing NH3 but composed of SiH4/N2/helium (He). The film forming temperature is set at from 200 to 350° C. More ideally, a flow rate ratio of He to SiH4 is set at from 100 to 125.

Abstract translation: 为了提供能够形成具有良好绝缘性能的氮化硅膜作为MTJ元件的保护膜的半导体器件的制造方法，而不会劣化MTJ元件的性质。 本发明的方法包括以下步骤：在使用平板等离子体CVD装置作为成膜装置的同时，在包括MTJ元件部分（MTJ元件和上电极）的整个表面上形成氮化硅膜，以及不含 NH3，但由SiH4 / N2 /氦（He）组成。 成膜温度设定在200〜350℃。更理想的是，将He与SiH4的流量比设定为100〜125。

公开(公告)号：US20090047757A1

公开(公告)日：2009-02-19

申请号：US12253510

申请日：2008-10-17

Applicant: Mikio TSUJIUCHI ,  Toshiaki IWAMATSU ,  Takashi IPPOSHI

Inventor： Mikio TSUJIUCHI ,  Toshiaki IWAMATSU ,  Takashi IPPOSHI

IPC: H01L21/336

CPC classification number: H01L29/458 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78609

Abstract: In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer in the SOI layer formed on the buried oxide film layer (BOX layer). An isolation insulating layer is a partial trench isolation which has not reached a BOX layer, and source and drain regions include the first and the second impurity ion which differs in a mass number mutually.

Abstract translation: 在SOI衬底中形成的元件之间的隔离部分沟槽隔离的半导体器件中，针对晶体管的源极漏极的电阻降低和泄漏电流的降低。 在形成在掩埋氧化膜层（BOX层）上的SOI层中的隔离绝缘层规定的有源区域中形成MOS晶体管。 隔离绝缘层是尚未到达BOX层的部分沟槽隔离，源区和漏区包括彼此相互质量数不同的第一和第二杂质离子。

公开(公告)号：US20070176235A1

公开(公告)日：2007-08-02

申请号：US11627167

申请日：2007-01-25

Applicant: Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

Inventor： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: In a semiconductor device, a body thick film transistor and a body thin film transistor having a different body film thickness are formed on the same SOI substrate (silicon support substrate, buried oxide film and silicon layer). The body film is formed to be relatively thick in the body thick film transistor, which has a recess structure where the level of the surface of the source/drain regions is lower than the level of the surface of the body region, and thus, the SOI film in the source/drain regions is formed to be as thin as the SOI film in the body thin film transistor. On the other hand, the entirety of the SOI film is formed to have a relatively thin film thickness in the body thin film transistor. In addition, the source/drain regions are formed to penetrate through the silicon layer.

Abstract translation: 在半导体器件中，在相同的SOI衬底（硅支撑衬底，掩埋氧化物膜和硅层）上形成具有不同体膜厚度的体积薄膜晶体管和体薄膜晶体管。 体膜形成为比较厚的体膜厚晶体管，其具有凹陷结构，其中源/漏区的表面的水平低于体区的表面的水平，因此， 源极/漏极区域中的SOI膜形成为与体薄膜晶体管中的SOI膜一样薄。 另一方面，在体薄膜晶体管中，整个SOI膜形成为具有较薄的膜厚。 此外，源极/漏极区域形成为穿透硅层。

公开(公告)号：US20060289904A1

公开(公告)日：2006-12-28

申请号：US11425072

申请日：2006-06-19

Applicant: Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

Inventor： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC: H01L29/76

CPC classification number: H01L29/458 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78609

Abstract: In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer in the SOI layer formed on the buried oxide film layer (BOX layer). An isolation insulating layer is a partial trench isolation which has not reached a BOX layer, and source and drain regions include the first and the second impurity ion which differs in a mass number mutually.

公开(公告)号：US20060180861A1

公开(公告)日：2006-08-17

申请号：US11341444

申请日：2006-01-30

Applicant: Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

Inventor： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L29/66772 ,  H01L29/78615

Abstract: In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.

Abstract translation: 在半导体器件中，在由SOI衬底构成的SOI衬底的顶部上设置栅电极，杂质扩散区域，体电位固定区域，第一绝缘体和虚设栅电极，所述SOI衬底由下面的硅衬底，埋入绝缘体和 半导体层。 杂质扩散区域是通过在栅电极周围的半导体层中注入第一导电类型的杂质形成的区域。 体电位固定区域是沿着栅电极的长度的延长线的方向设置的区域，并且注入第二导电类型的杂质。 至少在体电位固定区域和栅电极之间的部分形成第一绝缘体。 虚设栅电极设置在体电位固定区与栅电极之间的第一绝缘体上。

公开(公告)号：US20050101070A1

公开(公告)日：2005-05-12

申请号：US10978796

申请日：2004-11-02

Applicant: Mikio Tsujiuchi ,  Toshiaki Iwamatsu

Inventor： Mikio Tsujiuchi ,  Toshiaki Iwamatsu

IPC: H01L21/76 ,  H01L21/322 ,  H01L21/336 ,  H01L21/762 ,  H01L21/00

CPC classification number: H01L29/66772 ,  H01L21/3226 ,  H01L21/76283

Abstract: An SOI substrate is formed of a silicon oxide substrate and a silicon film. A surface of the silicon film is oxidized and a silicon oxide film is thereby formed. A polycrystalline silicon and a silicon nitride film are formed on the silicon oxide film in this order. Then, a trench is formed in a region. The trench is filled with an insulating material, e.g., a silicon oxide film.

Abstract translation: SOI衬底由氧化硅衬底和硅膜形成。 硅膜的表面被氧化，从而形成氧化硅膜。 依次在氧化硅膜上形成多晶硅和氮化硅膜。 然后，在一个区域中形成沟槽。 沟槽填充有绝缘材料，例如氧化硅膜。

公开(公告)号：US20050037524A1

公开(公告)日：2005-02-17

申请号：US10949451

申请日：2004-09-27

Applicant: Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

Inventor： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

IPC: H01L21/66 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612

Abstract: The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

公开(公告)号：US08350331B2

公开(公告)日：2013-01-08

申请号：US11627167

申请日：2007-01-25

Applicant: Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

Inventor： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

IPC: H01L21/70

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: In a semiconductor device, a body thick film transistor and a body thin film transistor having a different body film thickness are formed on the same SOI substrate (silicon support substrate, buried oxide film and silicon layer). The body film is formed to be relatively thick in the body thick film transistor, which has a recess structure where the level of the surface of the source/drain regions is lower than the level of the surface of the body region, and thus, the SOI film in the source/drain regions is formed to be as thin as the SOI film in the body thin film transistor. On the other hand, the entirety of the SOI film is formed to have a relatively thin film thickness in the body thin film transistor. In addition, the source/drain regions are formed to penetrate through the silicon layer.

Abstract translation: 在半导体器件中，在相同的SOI衬底（硅支撑衬底，掩埋氧化物膜和硅层）上形成具有不同体膜厚度的体积薄膜晶体管和体薄膜晶体管。 体膜形成为比较厚的体膜厚晶体管，其具有凹陷结构，其中源/漏区的表面的水平低于体区的表面的水平，因此， 源极/漏极区域中的SOI膜形成为与体薄膜晶体管中的SOI膜一样薄。 另一方面，在体薄膜晶体管中，整个SOI膜形成为具有较薄的膜厚。 此外，源极/漏极区域形成为穿透硅层。

公开(公告)号：US08264053B2

公开(公告)日：2012-09-11

申请号：US12474974

申请日：2009-05-29

Applicant: Keisuke Tsukamoto ,  Mikio Tsujiuchi

Inventor： Keisuke Tsukamoto ,  Mikio Tsujiuchi

IPC: H01L29/82 ,  G11C11/02

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

Abstract: To provide a semiconductor device that has an improved adhesion between a bottom conductive layer and a protection film protecting an MTJ element. This semiconductor device includes a bottom electrode formed over a semiconductor substrate, an MTJ element part formed over a part of the bottom electrode by lamination of a bottom magnetic film, an insulating film, a top magnetic film, and a top electrode in this order, and a protection film formed over the bottom electrode so as to cover the MTJ element part, wherein the bottom electrode is formed by amorphized metal nitride and the protection film is formed by an insulating film containing nitrogen.

Abstract translation: 提供一种在底部导电层和保护MTJ元件的保护膜之间具有改善的粘合性的半导体器件。 该半导体装置包括形成在半导体衬底上的底部电极，通过层叠底部磁性膜，绝缘膜，顶部磁性膜和顶部电极而形成在底部电极的一部分上的MTJ元件部分， 以及形成在底部电极上以覆盖MTJ元件部分的保护膜，其中底部电极由非晶态金属氮化物形成，并且保护膜由含氮的绝缘膜形成。