公开(公告)号：US08492847B2

公开(公告)日：2013-07-23

申请号：US13341421

申请日：2011-12-30

Applicant: Tatsunori Murata ,  Yuki Koide

Inventor： Tatsunori Murata ,  Yuki Koide

IPC: H01L21/70 ,  H01L21/4763

CPC classification number: H01L29/7843 ,  H01L21/2686 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: Over a semiconductor substrate, a silicon nitride film is formed so as to cover n-channel MISFETs. The silicon nitride film is a laminate film which may be made of first, second, and third silicon nitride films. The total film thickness of the first and second silicon nitride films is smaller than half a spacing between a first sidewall spacer and a second sidewall spacer. After being deposited, the first and second silicon nitride films are subjected to treatments to have increased tensile stresses. The total film thickness of the first, second, and third silicon nitride films is not less than half the spacing between the first and second sidewall spacers. The third silicon nitride film is not subjected to any tensile-stress-increasing treatment, or may be subjected to a lesser amount of such treatment.

Abstract translation: 在半导体衬底上形成氮化硅膜以覆盖n沟道MISFET。 氮化硅膜是可由第一，第二和第三氮化硅膜制成的层压膜。 第一和第二氮化硅膜的总膜厚度小于第一侧壁间隔物和第二侧壁间隔物之间​​的间隔的一半。 沉积后，对第一和第二氮化硅膜进行处理以增加拉伸应力。 第一，第二和第三氮化硅膜的总膜厚度不小于第一和第二侧壁间隔物之间​​的间距的一半。 第三氮化硅膜不经受任何拉伸应力增加处理，或者可以进行较少量的这种处理。

公开(公告)号：US08415756B2

公开(公告)日：2013-04-09

申请号：US12870486

申请日：2010-08-27

Applicant: Keisuke Tsukamoto ,  Shinya Hirano ,  Yuichiro Fujiyama ,  Tatsunori Murata

Inventor： Keisuke Tsukamoto ,  Shinya Hirano ,  Yuichiro Fujiyama ,  Tatsunori Murata

IPC: H01L29/82

CPC classification number: H01L27/105 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: There are provided a semiconductor device in which short circuit failures in magnetic resistor elements and the like are reduced, and a method of manufacturing the same. An interlayer insulating film in which memory cells are formed is formed such that the upper surface of the portion of the interlayer insulating film located in a memory cell region where the magnetic resistor elements are formed is at a position lower than that of the upper surface of the portion of the interlayer insulating film located in a peripheral region. Another interlayer insulating film is formed so as to cover the magnetic resistor elements. In the another interlayer insulating film, formed are bit lines electrically coupled to the magnetic resistor elements. Immediately below the magnetic resistor elements, formed are digit lines.

Abstract translation: 提供一种半导体器件，其中减小了电阻元件等中的短路故障及其制造方法。 其中形成存储单元的层间绝缘膜形成为使得位于形成有磁阻元件的存储单元区域中的层间绝缘膜的部分的上表面位于比上表面的位置低的位置 层间绝缘膜的位于周边区域的部分。 形成另一层间绝缘膜以覆盖磁阻元件。 在另一个层间绝缘膜中，形成电耦合到磁阻元件的位线。 在磁阻电阻元件的正下方形成数位线。

公开(公告)号：US08084343B2

公开(公告)日：2011-12-27

申请号：US12977573

申请日：2010-12-23

Applicant: Tadashi Yamaguchi ,  Koyu Asai ,  Mahito Sawada ,  Kiyoteru Kobayashi ,  Tatsunori Murata ,  Satoshi Shimizu

Inventor： Tadashi Yamaguchi ,  Koyu Asai ,  Mahito Sawada ,  Kiyoteru Kobayashi ,  Tatsunori Murata ,  Satoshi Shimizu

IPC: H01L21/20

CPC classification number: H01L21/76802 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

Abstract translation: 为了阻止通过HDP-CVD等形成层间绝缘膜时产生的氢离子，从而抑制氢离子对器件的不利影响，在包括接触层，金属互连和层间绝缘的半导体器件中 在其上形成有栅电极的半导体衬底上，通过使用含氢原子的气体的偏压施加等离子体CVD在金属互连上形成层间绝缘膜，并且在金属互连的底层设置氮氧化硅膜， 层间绝缘膜。

公开(公告)号：US20110101431A1

公开(公告)日：2011-05-05

申请号：US12911558

申请日：2010-10-25

Applicant: Yosuke TAKEUCHI ,  Mikio Tsujiuchi ,  Tatsunori Murata

Inventor： Yosuke TAKEUCHI ,  Mikio Tsujiuchi ,  Tatsunori Murata

IPC: H01L29/82 ,  H01L21/8239

CPC classification number: H01L27/228 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76883

Abstract: To provide a technology capable of improving the property of an MRAM in a semiconductor device containing the MRAM.A plasma treatment is performed on the surface of an interlayer insulating film for which a wiring and a digit line are formed. Firstly, a semiconductor substrate is carried in a chamber, and a mixed gas that includes molecules containing nitrogen (ammonia gas) and inert molecules not containing nitrogen (hydrogen gas, helium, argon) is introduced into the chamber. On this occasion, the plasma treatment is performed by introducing the mixed gas under such a condition that the flow rate of the inert molecules not containing nitrogen is larger than that of the molecules containing nitrogen, and the mixed gas is turned into a plasma.

Abstract translation: 提供能够提高包含MRAM的半导体器件中MRAM性能的技术。 在形成布线和数字线的层间绝缘膜的表面上进行等离子体处理。 首先，将半导体基板载置在室内，将包含氮（氨）的分子和不含氮的惰性分子（氢气，氦，氩））的混合气体引入室内。 在这种情况下，通过在不含氮的惰性分子的流量比含有氮的分子的流量大的条件下引入混合气体进行等离子体处理，将混合气体变成等离子体。

公开(公告)号：US20100270634A1

公开(公告)日：2010-10-28

申请号：US12832505

申请日：2010-07-08

Applicant: Tatsunori MURATA ,  Mikio Tsujiuchi

Inventor： Tatsunori MURATA ,  Mikio Tsujiuchi

IPC: H01L29/82

CPC classification number: H01L27/224 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F41/302 ,  H01F41/307 ,  H01L43/08 ,  H01L43/12

Abstract: The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH3 or H2 as pretreatment. Thereafter, a tensile stress silicon nitride film to impose tensile stress on an MTJ device is formed over a clad layer and over an interlayer dielectric film where the clad layer is not formed. Successively, a compressive stress silicon nitride film to impose compressive stress on the MTJ device is formed over the tensile stress silicon nitride film. The conditions for forming the tensile stress silicon nitride film and the compressive stress silicon nitride film are as follows: a parallel plate type plasma CVD apparatus is used; the RF power is set in the range of 0.03 to 0.4 W/cm2; and the film forming temperature is set in the range of 200° C. to 350° C.

Abstract translation: 本发明使得可以获得：能够形成高可靠性上线的半导体器件，而对MTJ器件的磁性材料的性能没有有害影响; 及其制造方法。 使用可还原NH3或H2作为预处理进行等离子体处理。 此后，在覆层和覆盖层未形成的层间电介质膜上形成在MTJ器件上施加拉伸应力的拉伸应力氮化硅膜。 接着，在拉伸应力氮化硅膜上形成在MTJ装置上施加压应力的压应力氮化硅膜。 用于形成拉伸应力氮化硅膜和压缩应力氮化硅膜的条件如下：使用平行板型等离子体CVD装置; RF功率设定在0.03〜0.4W / cm 2的范围内; 成膜温度设定在200〜350℃的范围。

公开(公告)号：US20090294881A1

公开(公告)日：2009-12-03

申请号：US12424982

申请日：2009-04-16

Applicant: Tatsunori MURATA ,  Mikio Tsujiuchi

Inventor： Tatsunori MURATA ,  Mikio Tsujiuchi

IPC: H01L29/82 ,  H01L43/12

CPC classification number: H01L27/224 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F41/302 ,  H01F41/307 ,  H01L43/08 ,  H01L43/12

Abstract: The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH3 or H2 as pretreatment. Thereafter, a tensile stress silicon nitride film to impose tensile stress on an MTJ device is formed over a clad layer and over an interlayer dielectric film where the clad layer is not formed. Successively, a compressive stress silicon nitride film to impose compressive stress on the MTJ device is formed over the tensile stress silicon nitride film. The conditions for forming the tensile stress silicon nitride film and the compressive stress silicon nitride film are as follows: a parallel plate type plasma CVD apparatus is used; the RF power is set in the range of 0.03 to 0.4 W/cm2; and the film forming temperature is set in the range of 200° C. to 350° C.

Abstract translation: 本发明使得可以获得：能够形成高可靠性的上线而不会对MTJ装置的磁性材料的性质产生有害影响的半导体器件; 及其制造方法。 使用可还原NH3或H2作为预处理进行等离子体处理。 此后，在覆层和覆盖层未形成的层间电介质膜上形成在MTJ器件上施加拉伸应力的拉伸应力氮化硅膜。 接着，在拉伸应力氮化硅膜上形成在MTJ装置上施加压应力的压应力氮化硅膜。 用于形成拉伸应力氮化硅膜和压缩应力氮化硅膜的条件如下：使用平行板型等离子体CVD装置; RF功率设定在0.03〜0.4W / cm 2的范围内; 成膜温度设定在200〜350℃的范围。

公开(公告)号：US20110092037A1

公开(公告)日：2011-04-21

申请号：US12977573

申请日：2010-12-23

Applicant: Tadashi Yamaguchi ,  Koyu Asai ,  Mahito Sawada ,  Kiyoteru Kobayashi ,  Tatsunori Murata ,  Satoshi Shimizu

Inventor： Tadashi Yamaguchi ,  Koyu Asai ,  Mahito Sawada ,  Kiyoteru Kobayashi ,  Tatsunori Murata ,  Satoshi Shimizu

IPC: H01L21/336

CPC classification number: H01L21/76802 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

Abstract translation: 为了阻止通过HDP-CVD等形成层间绝缘膜时产生的氢离子，从而抑制氢离子对器件的不利影响，在包括接触层，金属互连和层间绝缘的半导体器件中 在其上形成有栅电极的半导体衬底上，通过使用含氢原子的气体的偏压施加等离子体CVD在金属互连上形成层间绝缘膜，并且在金属互连的底层设置氮氧化硅膜， 层间绝缘膜。

公开(公告)号：US07772662B2

公开(公告)日：2010-08-10

申请号：US12424982

申请日：2009-04-16

Applicant: Tatsunori Murata ,  Mikio Tsujiuchi

Inventor： Tatsunori Murata ,  Mikio Tsujiuchi

IPC: H01L29/82

CPC classification number: H01L27/224 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F41/302 ,  H01F41/307 ,  H01L43/08 ,  H01L43/12

Abstract: The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH3 or H2 as pretreatment. Thereafter, a tensile stress silicon nitride film to impose tensile stress on an MTJ device is formed over a clad layer and over an interlayer dielectric film where the clad layer is not formed. Successively, a compressive stress silicon nitride film to impose compressive stress on the MTJ device is formed over the tensile stress silicon nitride film. The conditions for forming the tensile stress silicon nitride film and the compressive stress silicon nitride film are as follows: a parallel plate type plasma CVD apparatus is used; the RF power is set in the range of 0.03 to 0.4 W/cm2; and the film forming temperature is set in the range of 200° C. to 350° C.

Abstract translation: 本发明使得可以获得：能够形成高可靠性的上线而不会对MTJ装置的磁性材料的性质产生有害影响的半导体器件; 及其制造方法。 使用可还原NH3或H2作为预处理进行等离子体处理。 此后，在覆层和覆盖层未形成的层间电介质膜上形成在MTJ器件上施加拉伸应力的拉伸应力氮化硅膜。 接着，在拉伸应力氮化硅膜上形成在MTJ装置上施加压应力的压应力氮化硅膜。 用于形成拉伸应力氮化硅膜和压缩应力氮化硅膜的条件如下：使用平行板型等离子体CVD装置; RF功率设定在0.03〜0.4W / cm 2的范围内; 并且成膜温度设定在200℃至350℃的范围内。

公开(公告)号：US20090289367A1

公开(公告)日：2009-11-26

申请号：US12472100

申请日：2009-05-26

Applicant: Daisuke KODAMA ,  Shoichi Fukui ,  Hiroshi Miyazaki ,  Tatsunori Murata

Inventor： Daisuke KODAMA ,  Shoichi Fukui ,  Hiroshi Miyazaki ,  Tatsunori Murata

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/3148 ,  H01L21/318 ,  H01L21/76832 ,  H01L23/53295 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A copper interconnection layer is formed in an interconnection trench at a surface of an interlayer insulating film. A diffusion preventing insulating film is formed to cover the copper interconnection layer and is made of at least one of SiC and SiCN. An insulating film is formed on the copper interconnection layer with the diffusion preventing insulating film interposed and is made of SiN.

Abstract translation: 在层间绝缘膜的表面的互连沟槽中形成铜互连层。 形成扩散防止绝缘膜以覆盖铜互连层，并且由SiC和SiCN中的至少一种制成。 在铜互连层上形成有绝缘膜，其中扩散防止绝缘膜插入并由SiN制成。

公开(公告)号：US20090269860A1

公开(公告)日：2009-10-29

申请号：US12411665

申请日：2009-03-26

Applicant: Tatsunori MURATA ,  Mikio Tsujiuchi ,  Ryoji Matsuda

Inventor： Tatsunori MURATA ,  Mikio Tsujiuchi ,  Ryoji Matsuda

IPC: H01L43/12

CPC classification number: H01L27/228 ,  G11C11/16

Abstract: To provide a manufacturing method of a semiconductor device capable of forming, as a protective film of an MTJ element, a silicon nitride film having good insulation properties without deteriorating the properties of the MTJ element. The method of the invention includes steps of forming a silicon nitride film over the entire surface including an MTJ element portion (MTJ element and an upper electrode) while using a parallel plate plasma CVD apparatus as a film forming apparatus and a film forming gas not containing NH3 but composed of SiH4/N2/helium (He). The film forming temperature is set at from 200 to 350° C. More ideally, a flow rate ratio of He to SiH4 is set at from 100 to 125.

Abstract translation: 为了提供能够形成具有良好绝缘性能的氮化硅膜作为MTJ元件的保护膜的半导体器件的制造方法，而不会劣化MTJ元件的性质。 本发明的方法包括以下步骤：在使用平板等离子体CVD装置作为成膜装置的同时，在包括MTJ元件部分（MTJ元件和上电极）的整个表面上形成氮化硅膜，以及不含 NH3，但由SiH4 / N2 /氦（He）组成。 成膜温度设定在200〜350℃。更理想的是，将He与SiH4的流量比设定为100〜125。