公开(公告)号：US09570512B2

公开(公告)日：2017-02-14

申请号：US14960595

申请日：2015-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L21/4763 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line.

Abstract translation: 在支撑衬底上形成电阻随机存取存储器（RRAM）结构，并且包括第一电极和第二电极。 第一电极由支撑衬底上的硅化物翅片和覆盖硅化物翅片的第一金属衬垫层制成。 具有可配置电阻性能的电介质材料层覆盖第一金属衬垫的至少一部分。 第二电极由覆盖电介质材料层的第二金属衬垫层和与第二金属衬垫层接触的金属填充物制成。 非易失性存储单元包括电连接在存取晶体管和位线之间的RRAM结构。

公开(公告)号：US20160365456A1

公开(公告)日：2016-12-15

申请号：US14739634

申请日：2015-06-15

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/788 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7883 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

Abstract translation: 半浮栅晶体管被实现为内置于硅衬底上的垂直FET，其中源极，漏极和沟道彼此垂直对准。 源极和漏极之间的电流流动受到控制栅极和半浮栅的影响。 可以对垂直半浮栅晶体管的源极，漏极和控制栅极端子中的每一个进行正面接触。 垂直半浮栅FET还包括垂直隧道FET和垂直二极管。 垂直半浮栅FET的制造与常规CMOS制造工艺兼容，包括替代金属栅极工艺。 与传统的平面器件相比，低功耗操作允许垂直半浮栅FET提供高电流密度。

公开(公告)号：US20160322479A1

公开(公告)日：2016-11-03

申请号：US14698921

申请日：2015-04-29

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Salih Muhsin Celik

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/51 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66977 ,  H01L29/0649 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/165 ,  H01L29/4941 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7851

Abstract: A tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source region, a drain region and a channel region between the source region and drain region. A gate electrode straddles over the fin at the channel region. Sidewall spacers are provided on each side of the gate electrode. The source of the transistor is made from an epitaxial germanium content source region grown from the source region of the fin and doped with a first conductivity type. The drain of the transistor is made from an epitaxial silicon content drain region grown from the drain region of the fin and doped with a second conductivity type.

Abstract translation: 隧道场效应晶体管由支撑基板上的半导体材料的翅片形成。 半导体材料的鳍片包括源极区域，漏极区域和源极区域与漏极区域之间的沟道区域。 栅极电极横跨在通道区域上的翅片上。 在栅电极的每一侧设置侧壁间隔物。 晶体管的源极由从鳍片的源极区域生长并掺杂有第一导电类型的外延锗含量源区域制成。 晶体管的漏极由从鳍片的漏极区域生长并掺杂有第二导电类型的外延硅含量漏极区域制成。

公开(公告)号：US09419111B2

公开(公告)日：2016-08-16

申请号：US14748270

申请日：2015-06-24

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Prasanna Khare ,  Nicolas Loubet

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417 ,  H01L21/225

CPC classification number: H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US09368411B2

公开(公告)日：2016-06-14

申请号：US14596625

申请日：2015-01-14

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/84

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/823821 ,  H01L21/845

Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made on the bottom portion to produce a silicon-germanium region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.

Abstract translation: 由硅半导体材料形成的SOI衬底层包括相邻的第一和第二区域。 去除第二区域中的硅衬底层的一部分，使得第二区域保持由硅半导体材料制成的底部。 硅 - 锗半导体材料的外延生长在底部制成以产生硅 - 锗区。 图案化硅区域以限定第一（例如，n沟道）导电类型的FinFET的第一鳍结构。 硅 - 锗区域也被图案化以限定第二（例如p沟道）导电类型的FinFET的第二鳍结构。

公开(公告)号：US20160118305A1

公开(公告)日：2016-04-28

申请号：US14942504

申请日：2015-11-16

Applicant: STMicroelectronics, Inc.

Inventor： Walter Kleemeier ,  Qing Liu

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/84 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/778 ,  H01L29/7789 ,  H01L29/7838

Abstract: An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.

Abstract translation: 集成电路包括支撑具有源极区和漏极区的晶体管的衬底。 晶体管的源极区和漏极区存在高掺杂浓度的δ掺杂层。 一组触点延伸穿过覆盖晶体管的预金属介电层。 硅化物区域设置在该组触点的底部。 硅化物区域由接触底部存在的金属与晶体管的源极区域和漏极区域上的高掺杂浓度δ-掺杂层之间的水化反应形成。

公开(公告)号：US09123809B2

公开(公告)日：2015-09-01

申请号：US14494979

申请日：2014-09-24

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L21/266 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/7849

Abstract: A transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.

Abstract translation: 晶体管包括主体和构造成对身体的一部分施加应力的半导体区域。 例如，施加晶体管的沟道可以增加沟道中载流子的迁移率，从而可以降低晶体管的“导通”电阻。 例如，可以掺杂PFET的衬底，源极/漏极区域或者衬底和源/漏极区域，以对沟道进行压缩应力，从而增加沟道中空穴的迁移率。 或者，可以掺杂NFET的衬底，源极/漏极区域或衬底和源极/漏极区域两者以使通道拉伸应力，以增加沟道中电子的迁移率。

公开(公告)号：US20150108573A1

公开(公告)日：2015-04-23

申请号：US14060874

申请日：2013-10-23

Applicant: GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0886

Abstract: A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures.

Abstract translation: 制造半导体器件的方法可以包括在衬底上形成交替的第一和第二半导体层的至少一个叠层。 第一半导体层可以包括第一半导体材料，第二半导体层可以包括第二半导体材料。 第一半导体材料可以相对于第二半导体材料可选择性地蚀刻。 该方法还可以包括去除至少一个堆叠和衬底的部分以限定其暴露的侧壁，在暴露的侧壁上形成相应的间隔物，蚀刻通过至少一个堆叠和衬底的凹槽以限定多个间隔开的柱，选择性蚀刻 来自多个柱的第一半导体材料离开第二半导体材料结构，在相对端通过相应的间隔件支撑，并且形成与第二半导体材料结构相邻的至少一个栅极。

公开(公告)号：US11515418B2

公开(公告)日：2022-11-29

申请号：US16886193

申请日：2020-05-28

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/267 ,  H01L29/737 ,  H01L27/092 ,  H01L29/739 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

公开(公告)号：US10886386B2

公开(公告)日：2021-01-05

申请号：US15806160

申请日：2017-11-07

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu

IPC: H01L21/82 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.