公开(公告)号：US09893187B2

公开(公告)日：2018-02-13

申请号：US15342008

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Chris Bowen ,  Kiyotaka Imai ,  Mark S. Rodder

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7869

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a dummy gate is deposited on the fin, and processed, e.g., by plasma doping and annealing, to cause stress in the dummy gate. Deep source drain (SD) recesses are formed, resulting in strain in the channel, and SD structures are formed to anchor the ends of the fin. The dummy gate is then removed.

公开(公告)号：US09831323B2

公开(公告)日：2017-11-28

申请号：US15267134

申请日：2016-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Robert Christopher Bowen ,  Borna J. Obradovic ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/201 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/04 ,  H01L21/465

CPC classification number: H01L29/6681 ,  H01L21/02439 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02485 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/465 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/7848 ,  H01L29/7853

Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack includes a plurality of sacrificial layers in which each sacrificial layer has a first lattice parameter; and at least one channel layer that has a second lattice parameter in which the first lattice parameter is less than or equal to the second lattice parameter, and each channel layer is disposed between and in contact with two sacrificial layers and includes a compressive strain or a neutral strain based on a difference between the first lattice parameter and the second lattice parameter.

公开(公告)号：US20170338346A1

公开(公告)日：2017-11-23

申请号：US15342003

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7869

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a sacrificial epitaxial gate stressor is deposited on the fin, causing strain in the fin. SD structures are then formed to anchor the ends of the fin, and the sacrificial epitaxial gate stressor is removed.

公开(公告)号：US20170271477A1

公开(公告)日：2017-09-21

申请号：US15340827

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dharmendar Reddy Palle ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L29/167 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66553 ,  H01L29/0673 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method of forming a horizontal nanosheet device or a horizontal nanowire device includes forming a dummy gate and a series of external spacers on a stack including an alternating arrangement of sacrificial layers and channel layers, deep etching portions of the stack between the external spacers to form electrode recesses for a source electrode and a drain electrode, performing an etch-back on portions of the sacrificial layers to form internal spacer recesses above and below each of the channel layers, forming doped internal spacers in the internal spacer recesses, and forming doped extension regions of the source electrode and the drain electrode by outdiffusion of dopants from the doped internal spacers. The method may also include epitaxially regrowing the source electrode and the drain electrode in the electrode recesses.

公开(公告)号：US09768062B1

公开(公告)日：2017-09-19

申请号：US15276748

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  David Seo ,  Kota Oikawa ,  Kim Changhwa ,  Rwik Sengupta ,  Mark S. Rodder

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/785

Abstract: A method for forming a low parasitic capacitance contact to a source-drain structure of a fin field effect transistor device. In some embodiments the method includes etching a long trench down to the source-drain structure, the trench being sufficiently long to extend across all the of source-drain regions of the device. A conductive layer is formed on the source-drain structure, and the trench is filled with a first fill material. A second, narrower trench is opened along a portion of the length of the first trench, and filled with a second fill material. The first fill material may be conductive, and may form the contact. If the first fill material is not conductive, a third trench may be opened, in the portion of the first trench not filled with the second fill material, and filled with a conductive material, to form the contact.

公开(公告)号：US20170098661A1

公开(公告)日：2017-04-06

申请号：US15210867

申请日：2016-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Rwik Sengupta ,  Wei-E Wang ,  Ryan Hatcher ,  Mark S. Rodder

IPC: H01L27/12 ,  H01L23/528 ,  H01L29/24 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/84 ,  H01L23/522 ,  H01L29/45

CPC classification number: H01L27/12 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/78681

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.

公开(公告)号：US09583590B2

公开(公告)日：2017-02-28

申请号：US14698402

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66522 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include InyGa1−yAs, and y is in a range of about 0.3 to about 0.5.

Abstract translation: 提供了形成finFET的方法。 所述方法可以包括在衬底上形成包括铟（In）的鳍状沟道区域，形成与衬底上的沟道区相邻的深源极/漏极区域，并在沟道区域和深度之间形成源极/漏极延伸区域 源/漏区。 源极/漏极延伸区域的相对侧壁可以分别接触沟道区域和深源极/漏极区域，并且源极/漏极延伸区域可以包括In y Ga 1-y As，y在约0.3至约0.5的范围内。

公开(公告)号：US09525053B2

公开(公告)日：2016-12-20

申请号：US14304008

申请日：2014-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Mark S. Rodder ,  Robert C. Bowen ,  Jorge A. Kittl

IPC: H01L29/04 ,  H01L29/778 ,  H01L29/12 ,  H01L29/78 ,  H01L29/267 ,  H01L29/66 ,  H01L29/06 ,  H01L29/22

CPC classification number: H01L29/7781 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/122 ,  H01L29/22 ,  H01L29/267 ,  H01L29/66431 ,  H01L29/785

Abstract: Integrated circuit devices including strained channel regions and methods of forming the same are provided. The integrated circuit devices may include enhancement-mode field effect transistors. The enhancement-mode field effect transistors may include a quantum well channel region having a well thickness Tw sufficient to yield a strain-induced splitting of a plurality of equivalent-type electron conduction states therein to respective unequal energy levels including a lowermost energy level associated with a lowermost surface roughness scattering adjacent a surface of the channel region when, the surface is biased into a state of inversion.

Abstract translation: 提供包括应变通道区域的集成电路器件及其形成方法。 集成电路器件可以包括增强型场效应晶体管。 增强型场效应晶体管可以包括具有足够的阱厚度Tw的量子阱沟道区，其足以产生其中的多个等效型电子传导状态的应变引起的分裂到相应的不等能级，包括与 当表面被偏置到反转状态时，邻近通道区域的表面的最低表面粗糙度散射。

公开(公告)号：US09331176B2

公开(公告)日：2016-05-03

申请号：US13870471

申请日：2013-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Dong-Won Kim

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7856

Abstract: Methods of forming a fin-shaped Field Effect Transistor (FinFET) are provided. The methods may include selectively incorporating source/drain extension-region dopants into source and drain regions of a semiconductor fin, using a mask to block incorporation of the source/drain extension-region dopants into at least portions of the semiconductor fin. The methods may include removing portions of the source and drain regions of the semiconductor fin to define recesses therein. The methods may include epitaxially growing source and drain regions from the recesses in the semiconductor fin.

Abstract translation: 提供了形成鳍状场效应晶体管（FinFET）的方法。 所述方法可以包括使用掩模来将源极/漏极延伸区掺杂物选择性地并入到半导体鳍片的源极和漏极区域中，以阻止源极/漏极延伸区掺杂物掺入到半导体鳍片的至少部分中。 所述方法可以包括去除半导体鳍片的源区和漏区的部分以在其中限定凹陷。 所述方法可以包括从半导体鳍片中的凹部外延生长源极和漏极区域。

公开(公告)号：US20160111284A1

公开(公告)日：2016-04-21

申请号：US14918954

申请日：2015-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L21/283 ,  H01L21/306

CPC classification number: H01L29/0669 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L29/0665 ,  H01L29/1054 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7783

Abstract: Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial stack of one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing, and wherein the sacrificial layer An is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A; proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that to hold the nanosheets in place after selective etch of the sacrificial layers; and selectively removing sacrificial layers A to all non-sacrificial layers B and C, while the remaining layers in the stack are held in place by the pillar structures so that after removal of the sacrificial layers An, each of the sub-stacks contains the non-sacrificial layers B and C.

Abstract translation: 示例性实施例提供制造具有一个或多个子堆叠的纳米片堆叠结构。 示例性实施例的方面包括：生长一个或多个子堆叠的外延晶体初始堆叠，每个子堆叠具有至少三个层，牺牲层A和至少两个不同的非牺牲层B和C 具有不同的材料性质，其中非牺牲层B和C层保持低于在所有加工期间对应于亚稳态的热力学或动力学临界厚度，并且其中牺牲层An仅被放置在每个的顶部或底部 并且每个子堆叠使用牺牲层A之一连接到顶部或底部的相邻子堆叠; 继续纳米片装置的制造流程，使得在外延晶体堆叠的每个端部处形成柱结构，以在选择性蚀刻牺牲层之后将纳米片保持在适当位置; 并且将牺牲层A选择性地去除所有非牺牲层B和C，而堆叠中的其余层被柱结构保持就位，使得在去除牺牲层An之后，每个子堆包含非牺牲层 - 层B和C.