公开(公告)号：US12014923B2

公开(公告)日：2024-06-18

申请号：US18213120

申请日：2023-06-22

申请人： ATOMERA INCORPORATED

发明人： Hideki Takeuchi ,  Robert J. Mears

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L29/10 ,  H01L29/15 ,  H01L29/78

CPC分类号： H01L21/02507 ,  H01L21/0245 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7833

摘要： A method for making a radio frequency (RF) semiconductor device may include forming an RF ground plane layer on a semiconductor-on-insulator substrate and including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers including stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The method may further include forming a body above the RF ground plane layer, forming spaced apart source and drain regions adjacent the body and defining a channel region in the body, and forming a gate overlying the channel region.

公开(公告)号：US20240194787A1

公开(公告)日：2024-06-13

申请号：US18581153

申请日：2024-02-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/7855 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/045 ,  H01L2029/7858

摘要： A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

公开(公告)号：US20240194783A1

公开(公告)日：2024-06-13

申请号：US18064285

申请日：2022-12-12

申请人： GlobalFoundries U.S. Inc.

发明人： SHESH MANI PANDEY

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7824 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66681

摘要： A semiconductor device comprises a semiconductor layer over an insulator layer and a base layer under the insulator layer. A drain region comprises a well in the base layer, a doped region above and coupled with the well, a first drift region above and coupled with the first region, and a second drift region above the first doped region. The first doped region is at least partially in the insulator layer and the first drift region is at least partially in the semiconductor layer. A trench isolation structure is within the drain region and a gate stack is partially over the semiconductor layer and overlapping the first drift region.

公开(公告)号：US12009396B2

公开(公告)日：2024-06-11

申请号：US17266637

申请日：2020-04-22

申请人： INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.

发明人： Anbang Zhang ,  King Yuen Wong ,  Hao Li ,  Haoning Zheng ,  Jian Wang

IPC分类号： H01L29/417 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78

CPC分类号： H01L29/41766 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7838

摘要： A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional hole gas (2DHG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DHG.

公开(公告)号：US12009213B2

公开(公告)日：2024-06-11

申请号：US17591384

申请日：2022-02-02

申请人： ROHM CO., LTD.

发明人： Yuki Nakano

IPC分类号： H01L29/861 ,  H01L21/02 ,  H01L21/04 ,  H01L21/28 ,  H01L27/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872

CPC分类号： H01L21/049 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/044 ,  H01L21/28008 ,  H01L21/28264 ,  H01L27/04 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66045 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66446 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/0603

摘要： A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

公开(公告)号：US20240186412A1

公开(公告)日：2024-06-06

申请号：US18441118

申请日：2024-02-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Yu Chen ,  Wan-Hua Huang ,  Jing-Ying Chen ,  Kuo-Ming Wu

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/7835 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665

摘要： A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

公开(公告)号：US20240186400A1

公开(公告)日：2024-06-06

申请号：US18440347

申请日：2024-02-13

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： De-Fang Chen ,  Teng-Chun Tsai ,  Cheng-Tung Lin ,  Li-Ting Wang ,  Chun-Hung Lee ,  Ming-Ching Chang ,  Huan-Just Lin

IPC分类号： H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/6653 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L21/76224

摘要： According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

公开(公告)号：US12004354B2

公开(公告)日：2024-06-04

申请号：US17235343

申请日：2021-04-20

申请人： Micron Technology, Inc.

发明人： Durai Vishak Nirmal Ramaswamy

IPC分类号： H10B53/20 ,  H01L23/528 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L49/02 ,  H10B12/00 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B51/20 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H10B51/10 ,  H10B51/30 ,  H10B53/10 ,  H10B53/30

CPC分类号： H10B53/20 ,  H01L23/528 ,  H01L27/0688 ,  H01L28/60 ,  H01L28/90 ,  H01L29/0847 ,  H01L29/1037 ,  H10B12/03 ,  H10B12/05 ,  H10B12/30 ,  H10B12/48 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B51/20 ,  H01L21/02164 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H10B51/10 ,  H10B51/30 ,  H10B53/10 ,  H10B53/30

摘要： A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. An access-line pillar extends elevationally through the vertically-alternating tiers. The gate of individual of the transistors in different of the memory-cell tiers comprises a portion of the elevationally-extending access-line pillar. Other embodiments, including method, are disclosed.

公开(公告)号：US20240178675A1

公开(公告)日：2024-05-30

申请号：US18537620

申请日：2023-12-12

申请人： Navitas Semiconductor Limited

发明人： Daniel M. Kinzer ,  Santosh Sharma ,  Ju Jason Zhang

IPC分类号： H02J7/00 ,  H01L23/495 ,  H01L23/528 ,  H01L23/62 ,  H01L25/07 ,  H01L27/02 ,  H01L27/088 ,  H01L29/10 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H02M1/00 ,  H02M1/088 ,  H02M3/155 ,  H02M3/157 ,  H02M3/158 ,  H03K3/012 ,  H03K3/356 ,  H03K17/10 ,  H03K19/0185

CPC分类号： H02J7/00 ,  H01L23/49503 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/528 ,  H01L23/62 ,  H01L25/072 ,  H01L27/0248 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H02M1/088 ,  H02M3/157 ,  H02M3/1584 ,  H02M3/1588 ,  H03K3/012 ,  H03K3/356017 ,  H03K17/102 ,  H03K19/018507 ,  H01L2924/00 ,  H01L2924/0002 ,  H02M1/0048 ,  H02M3/155 ,  Y02B40/00 ,  Y02B70/10

摘要： GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

公开(公告)号：US20240178315A1

公开(公告)日：2024-05-30

申请号：US18059265

申请日：2022-11-28

申请人： Vanguard International Semiconductor Corporation

发明人： Wen-Shan LEE ,  Chung-Yeh LEE ,  Fu-Hsin CHEN

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/7806 ,  H01L21/26513 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor device includes a substrate having a first conductivity type, an epitaxial layer formed on the substrate, a well region extending from a top surface of the epitaxial layer into the epitaxial layer, a drift region formed in the epitaxial layer and in contact with the bottom surface of the well region, a gate structure and a conductive structure. The epitaxial layer has the first conductivity type, the well region has the second conductivity type, and the drift region has the first conductivity type. The gate structure that extends from the top surface of the epitaxial layer penetrates the well region and is in contact with the drift region. The conductive structure is formed in the drift region and disposed below the gate structure. A gate electrode of the gate structure is separated from the underlying conductive structure by the gate dielectric layer of the gate structure.