公开(公告)号：US20150228542A1

公开(公告)日：2015-08-13

申请号：US14698094

申请日：2015-04-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Chao Chiu ,  Chen-Yu Chen ,  Chih-Ming Lai ,  Ming-Feng Shieh ,  Nian-Fuh Cheng ,  Ru-Gun Liu ,  Wen-Chun Huang

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate.

Abstract translation: 提供包括在半导体衬底上形成心轴的半导体器件制造方法。 该方法继续包括使心轴氧化形成氧化区域，其中氧化区域邻接心轴的侧壁。 然后从半导体衬底去除心轴。 在去除心轴之后，使用氧化区域对形成在半导体衬底上的下层进行图案化。

公开(公告)号：US09070630B2

公开(公告)日：2015-06-30

申请号：US14090848

申请日：2013-11-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Gun Liu ,  Chung-Te Lin ,  Ming-Feng Shieh ,  Tsai-Sheng Gau ,  Shih-Ming Chang

IPC: H01L21/302 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/0338

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns.

公开(公告)号：US20150179435A1

公开(公告)日：2015-06-25

申请号：US14134027

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh-Han Wu ,  Chung-Ju Lee ,  Cheng-Hsiung Tsai ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Tien-I Bao ,  Shau-Lin Shue

IPC: H01L21/02 ,  H01L21/308 ,  H01L21/027

CPC classification number: H01L21/76816 ,  H01L21/02104 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802

Abstract: A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.

Abstract translation: 形成目标图案的方法包括在第一掩模上在衬底上形成多条线，并在该衬底上，多条线上以及多条线的侧壁上形成第一间隔层。 多条线被去除，从而在衬底上提供图案化的第一间隔层。 所述方法还包括在所述图案化的第一间隔层上以及所述图案化的第一间隔层的侧壁上方在所述衬底上形成第二间隔层，以及在所述第二间隔层上形成具有第二掩模的图案化材料层。 由此，图案化材料层和第二间隔层共同限定多个沟槽。

公开(公告)号：US20150111362A1

公开(公告)日：2015-04-23

申请号：US14057789

申请日：2013-10-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Feng Shieh ,  Weng-Hung Tseng ,  Tzung-Hua Lin ,  Hung-Chang Hsieh

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886

Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.

Abstract translation: 公开了制造鳍状场效应晶体管器件的方法。 该方法包括在基底上形成心轴特征并执行第一切割以去除心轴特征以形成第一空间。 该方法还包括执行第二切割以去除心轴特征的一部分以形成线端和端对端空间。 在第一次和第二次切割之后，使用芯棒特征蚀刻衬底，其中第一空间和端对端空间作为蚀刻掩模，以形成翅片。 沉积空间层以完全填充相邻散热片之间的空间并且覆盖与第一空间和端对端空间相邻的翅片的侧壁。 间隔层被蚀刻以在靠近第一空间和端对端空间的翅片上形成侧壁间隔物，并且在第一空间和端对端空间中形成隔离沟槽。

公开(公告)号：US20140273456A1

公开(公告)日：2014-09-18

申请号：US13911334

申请日：2013-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Feng Shieh ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Shih-Ming Chang

IPC: H01L21/308 ,  H01L21/306

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/30625

Abstract: A method of forming a target pattern includes forming a mandrel pattern on a substrate, the mandrel pattern having a line with a first dimension in a first direction and a second dimension in a second direction; forming a spacer around the mandrel pattern, the spacer having a first width; forming a cut pattern over the mandrel pattern and the spacer wherein the cut pattern partially overlaps the spacer on both sides of the line in the first direction; etching the mandrel pattern using the cut pattern as an etch mask, thereby defining a plurality of openings with sidewalls of the spacer, the cut pattern, and a portion of the mandrel pattern underneath the cut pattern; and reducing the first width of the spacer thereby to enlarge the plurality of openings.

Abstract translation: 形成目标图案的方法包括在基底上形成心轴图案，所述心轴图案具有在第一方向上具有第一尺寸的线和在第二方向上的第二尺寸的线; 在所述心轴图案周围形成间隔件，所述间隔件具有第一宽度; 在心轴图案和间隔物上形成切割图案，其中切割图案在第一方向上在线的两侧部分地与间隔物重叠; 使用切割图案蚀刻心轴图案作为蚀刻掩模，从而限定具有间隔件的侧壁，切割图案以及在切割图案下方的心轴图案的一部分的多个开口; 并且减小间隔物的第一宽度，从而扩大多个开口。

公开(公告)号：US20140256107A1

公开(公告)日：2014-09-11

申请号：US14286415

申请日：2014-05-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ming-Feng Shieh ,  Chang-Yun Chang ,  Hsin-Chih Chen

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/66636

Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate and forming a plurality of dummy gate structures in the substrate. The method further includes forming sidewall spacers on sidewalls of the dummy gate structures and forming a plurality of epitaxial growth regions between the dummy gate structures. After forming the plurality of epitaxial growth regions, one of the dummy gate structures is removed to form an isolation trench, which is filled with a dielectric layer to form an isolation feature. The remaining dummy gate structures are removed to form gate trenches, and gate structures are formed in the gate trenches.

Abstract translation: 形成半导体器件的方法包括提供半导体衬底并在衬底中形成多个虚拟栅极结构。 该方法还包括在虚拟栅极结构的侧壁上形成侧壁间隔物，并在虚拟栅极结构之间形成多个外延生长区域。 在形成多个外延生长区域之后，去除虚拟栅极结构之一以形成隔离沟槽，其中填充有电介质层以形成隔离特征。 去除剩余的虚拟栅极结构以形成栅极沟槽，并且栅极结构形成在栅极沟槽中。

公开(公告)号：US20130313646A1

公开(公告)日：2013-11-28

申请号：US13957108

申请日：2013-08-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Feng Shieh ,  Chih-Hao Yu ,  Chang-Yun Chang

IPC: H01L29/78

CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L21/845

Abstract: A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed. After the hard mask has been removed, the gate electrode layer may be separated into individual gate electrodes.

Abstract translation: 提供一种形成具有翅片的半导体器件的结构和方法。 在一个实施例中，使用硬掩模来图案化栅极电极层，然后将其去除。 在硬掩模被去除之后，栅极电极层可以分离成单独的栅电极。

公开(公告)号：US20130273750A1

公开(公告)日：2013-10-17

申请号：US13912936

申请日：2013-06-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Feng Shieh ,  Kuei-Liang Lu

IPC: H01L21/02

CPC classification number: H01L21/02002 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for aligning layers more accurately for FinFETs fabrication. An embodiment method includes forming a first pattern in a workpiece using a first photomask, forming a second pattern in the workpiece using a second photomask, the second photomask aligned to the first pattern, and aligning a third pattern to the first and the second patterns by aligning a first feature of the third pattern to a first feature of the first pattern in a first direction, and aligning a second feature of the third pattern to a first feature of the second pattern in a second direction orthogonal to the first direction.

Abstract translation: FinFET制造更准确地对准层的方法。 一种实施方式包括使用第一光掩模在工件中形成第一图案，使用第二光掩模在工件中形成第二图案，第二光掩模与第一图案对准，并且将第三图案与第一图案和第二图案对准 在第一方向上将第三图案的第一特征对准第一图案的第一特征，并且将第三图案的第二特征与第二图案的第一特征在与第一方向正交的第二方向上对准。

公开(公告)号：US11854820B2

公开(公告)日：2023-12-26

申请号：US16882063

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Gun Liu ,  Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Chih-Ming Lai ,  Chia-Ying Lee ,  Jyu-Horng Shieh ,  Ken-Hsien Hsieh ,  Ming-Feng Shieh ,  Shau-Lin Shue ,  Shih-Ming Chang ,  Tien-I Bao ,  Tsai-Sheng Gau

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/8234

CPC classification number: H01L21/3086 ,  H01L21/0217 ,  H01L21/0276 ,  H01L21/02186 ,  H01L21/02282 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/823431

Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.

公开(公告)号：US11735477B2

公开(公告)日：2023-08-22

申请号：US16880718

申请日：2020-05-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Feng Shieh ,  Hung-Chang Hsieh ,  Wen-Hung Tseng

IPC: H01L29/417 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/43 ,  H01L29/49 ,  H01L29/51 ,  H01L21/321 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L23/485 ,  H01L21/4763 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28141 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/7688 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76879 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53233 ,  H01L23/53257 ,  H01L27/0924 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L21/31055 ,  H01L21/4763 ,  H01L21/76852 ,  H01L21/76861 ,  H01L21/76865 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823828 ,  H01L23/53295 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.