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    RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE
    92.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE 有权
    电阻随机存取存储器（RRAM）结构

    公开(公告)号：US20160218283A1

    公开(公告)日：2016-07-28

    申请号：US14605023

    申请日：2015-01-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hai-Dang Trinh ,  Chia-Shiung Tsai ,  Chin-Wei Liang ,  Cheng-Yuan Tsai ,  Hsing-Lien Lin ,  Chin-Chieh Yang ,  Wen-Ting Chu

    IPC: H01L45/00

    CPC classification number: H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1675

    Abstract: A resistive random access memory (RRAM) cell with a high κ layer based on a group-V oxide and hafnium oxide is provided. The RRAM cell includes a bottom electrode layer, a group-V oxide layer arranged over the bottom electrode layer, and a hafnium oxide based layer arranged over and abutting the group-V oxide layer. The RRAM cell further includes a capping layer arranged over and abutting the hafnium oxide based layer, and a top electrode layer arranged over the capping layer. A method for manufacturing the RRAM cell is also provided.

    Abstract translation: 提供了一种基于V族氧化物和氧化铪的具有高κ层的电阻随机存取存储器（RRAM）单元。 RRAM单元包括布置在底部电极层上的底部电极层，V族氧化物层和布置在V族氧化物层上并与其邻接的基于氧化铪的层。 RRAM单元还包括布置在氧化铪基层上并邻接氧化铪层的覆盖层和布置在覆盖层上的顶部电极层。 还提供了制造RRAM单元的方法。

    HIGH YIELD RRAM CELL WITH OPTIMIZED FILM SCHEME
    93.
    发明申请
    HIGH YIELD RRAM CELL WITH OPTIMIZED FILM SCHEME 有权
    具有优化膜方案的高电平RRAM电池

    公开(公告)号：US20150287917A1

    公开(公告)日：2015-10-08

    申请号：US14592340

    申请日：2015-01-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Trinh Hai Dang ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai ,  Chin-Chieh Yang ,  Yu-Wen Liao ,  Wen-Ting Chu ,  Chia-Shiung Tsai

    IPC: H01L45/00

    CPC classification number: H01L45/1233 ,  H01L45/08 ,  H01L45/12 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1641 ,  H01L45/1675

    Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a good yield, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer, and forming a variable resistance dielectric data storage layer having a first thickness onto the bottom electrode. A capping layer is formed onto the dielectric data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness. A top electrode is formed over the capping layer, and an upper metal interconnect layer is formed over the top electrode.

    Abstract translation: 本公开涉及形成具有良好产量的电阻随机存取存储器（RRAM）单元的方法和相关联的装置。 在一些实施例中，通过在下金属互连层上形成底电极，并在底电极上形成具有第一厚度的可变电阻电介质数据存储层来执行该方法。 在电介质数据存储层上形成覆盖层。 封盖层的第二厚度在比第一厚度厚约2至约3倍的范围内。 在覆盖层上形成顶部电极，并且在顶部电极上形成上部金属互连层。

    Top Electrode Blocking Layer for RRAM Device
    95.
    发明申请
    Top Electrode Blocking Layer for RRAM Device 有权
    用于RRAM设备的顶部电极阻挡层

    公开(公告)号：US20150144859A1

    公开(公告)日：2015-05-28

    申请号：US14087082

    申请日：2013-11-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsia-Wei Chen ,  Wen-Ting Chu ,  Kuo-Chi Tu ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Yu-Wen Liao ,  Wen-Chun You ,  Sheng-Hung Shih

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1233 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/122 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1683

    Abstract: An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode.

    Abstract translation: 一种包括在衬底上形成的电阻随机存取存储器（RRAM）单元的集成电路器件。 RRAM单元包括具有上表面的顶电极。 阻挡层覆盖上表面的一部分。 通孔在电介质矩阵内在顶部电极上方延伸。 顶部电极的上表面包括与阻挡层接触的区域和与通孔相接合的区域。 与通孔相接的上表面的区域围绕与阻挡层相接的上表面区域。 阻挡层在处理期间是功能性的，以保护RRAM单元免受蚀刻损伤，同时以不妨碍上覆通孔和顶部电极之间的接触的方式构造。

    High electron affinity dielectric layer to improve cycling
    97.
    发明授权
    High electron affinity dielectric layer to improve cycling 有权

    公开(公告)号：US11696521B2

    公开(公告)日：2023-07-04

    申请号：US16939497

    申请日：2020-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-Yang Chen ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Wen-Ting Chu ,  Cheng-Jun Wu

    IPC: H01L45/00 ,  H10N70/00 ,  G11C13/00 ,  H10B63/00

    CPC classification number: H10N70/883 ,  G11C13/0007 ,  H10B63/00 ,  H10N70/021 ,  H10N70/841

    Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.

    Embedded ferroelectric memory cell
    98.
    发明授权
    Embedded ferroelectric memory cell 有权

    公开(公告)号：US11437084B2

    公开(公告)日：2022-09-06

    申请号：US17177627

    申请日：2021-02-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair

    IPC: H01L21/00 ,  G11C11/22 ,  H01L27/11592 ,  H01L27/1159 ,  H01L29/51

    Abstract: The present disclosure relates to a method of forming a memory structure. The method includes depositing a ferroelectric random access memory (FeRAM) stack over a substrate. The FeRAM stack has a ferroelectric layer and one or more conductive layers over the ferroelectric layer. The FeRAM stack is patterned to define an FeRAM device stack. A sidewall spacer is formed along a first side of the FeRAM device stack, and a select gate is formed along a side of the sidewall spacer that faces away from the FeRAM device stack. A source region is formed within the substrate and along a second side of the FeRAM device stack, and a drain region is formed within the substrate. The drain region is separated from the FeRAM device stack by the select gate.

    Electrode structure to improve RRAM performance
    100.
    发明授权
    Electrode structure to improve RRAM performance 有权

    公开(公告)号：US11329221B2

    公开(公告)日：2022-05-10

    申请号：US16693946

    申请日：2019-11-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Ting Chu ,  Tong-Chern Ong ,  Ying-Lang Wang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: The present disclosure, in some embodiments, relates to a method of forming a resistive random access memory (RRAM) device. The method includes forming one or more bottom electrode films over a lower interconnect layer within a lower inter-level dielectric layer. A data storage film having a variable resistance is formed above the one or more bottom electrode films. A lower top electrode film including a metal is over the data storage film, one or more oxygen barrier films are over the lower top electrode film, and an upper top electrode film including a metal nitride is formed over the one or more oxygen barrier films. The one or more oxygen barrier films include one or more of a metal oxide film and a metal oxynitride film. The upper top electrode film is formed to be completely confined over a top surface of the one or more oxygen barrier films.

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