公开(公告)号：US10079291B2

公开(公告)日：2018-09-18

申请号：US15145804

申请日：2016-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Kei-Wei Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66553 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor including a substrate, insulators, a gate stack, a seal spacer, a first offset spacer, and a second offset spacer is described. The substrate has fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and over the insulators. The seal spacer is located over the sidewall of the gate stack. The first offset spacer is located over the seal spacer. The second offset spacer is located over the first offset spacer.

公开(公告)号：US10002867B2

公开(公告)日：2018-06-19

申请号：US15062210

申请日：2016-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Ziwei Fang ,  Tsan-Chun Wang ,  Kei-Wei Chen

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.

公开(公告)号：US20170323971A1

公开(公告)日：2017-11-09

申请号：US15652271

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/223 ,  H01L21/265

CPC classification number: H01L29/7848 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/7834 ,  H01L29/785

Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.

公开(公告)号：US20170222051A1

公开(公告)日：2017-08-03

申请号：US15009834

申请日：2016-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/78 ,  H01L21/223 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7848 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/7834 ,  H01L29/785

Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.

公开(公告)号：US20240378362A1

公开(公告)日：2024-11-14

申请号：US18783508

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Shuo Liu ,  Chih-Chun Hsia ,  Hsin-Ting Chou ,  Kuanhua Su ,  William Weilun Hong ,  Chih Hung Chen ,  Kei-Wei Chen

IPC: G06F30/392 ,  G06F111/20 ,  G06T7/00

Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.

公开(公告)号：US20240274667A1

公开(公告)日：2024-08-15

申请号：US18644770

申请日：2024-04-24

Applicant: Taiwan Semiconductor Manufacturing co., Ltd

Inventor： Heng-Wen Ting ,  Kei-Wei Chen ,  Chii-Horng Li ,  Pei-Ren Jeng ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Chun-An Lin

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one or more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.

公开(公告)号：US11984323B2

公开(公告)日：2024-05-14

申请号：US17372705

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Chien Hou ,  Yu-Ting Yen ,  Cheng-Yu Kuo ,  Chih Hung Chen ,  William Weilun Hong ,  Kei-Wei Chen

IPC: H01L21/3105 ,  B24B37/04 ,  B24B37/20 ,  C02F1/469 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/31053 ,  B24B37/042 ,  B24B37/044 ,  B24B37/20 ,  H01L21/02065 ,  H01L21/31055 ,  H01L29/66545 ,  C02F1/4691

Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.

公开(公告)号：US20240149388A1

公开(公告)日：2024-05-09

申请号：US18410408

申请日：2024-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kei-Wei Chen ,  Chih Hung Chen

IPC: B24B37/015 ,  B24B37/20 ,  B24B37/30 ,  B24B53/017

CPC classification number: B24B37/015 ,  B24B37/20 ,  B24B37/30 ,  B24B53/017

Abstract: A method includes polishing a wafer on a polishing pad, performing conditioning on the polishing pad using a disk of a pad conditioner, and conducting a heat-exchange media into the disk. The heat-exchange media conducted into the disk has a temperature different from a temperature of the polishing pad.

公开(公告)号：US20230364734A1

公开(公告)日：2023-11-16

申请号：US18359180

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Chuan Su ,  Jeng-Chi Lin ,  Guan-Yi Lee ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: B24B37/20 ,  H01L21/306 ,  H01L21/321

CPC classification number: B24B37/20 ,  H01L21/30625 ,  H01L21/3212

Abstract: An embodiment is a polishing pad including a top pad and a sub pad that is below and contacting the top pad. The top pad includes top grooves along a top surface and microchannels extending from the top grooves to a bottom surface of the top pad. The sub pad includes sub grooves along a top surface of the sub pad.

公开(公告)号：US20230317519A1

公开(公告)日：2023-10-05

申请号：US18330466

申请日：2023-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76883 ,  H01L21/76825 ,  H01L23/5226 ,  H01L29/66795

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.