公开(公告)号：US20200303550A1

公开(公告)日：2020-09-24

申请号：US16895909

申请日：2020-06-08

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  Peijie Feng

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/165

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

公开(公告)号：US10247617B2

公开(公告)日：2019-04-02

申请号：US15246006

申请日：2016-08-24

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  Periannan Chidambaram ,  Bin Yang ,  Jiefeng Jeff Lin ,  Giridhar Nallapati ,  Bo Yu ,  Jie Deng ,  Jun Yuan ,  Stanley Seungchul Song

IPC: G01K7/01 ,  G01K7/24 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/66 ,  H01L23/528 ,  H01L49/02 ,  G01K7/18 ,  H01L23/34 ,  H01L23/522 ,  H01L27/06

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

公开(公告)号：US20190035796A1

公开(公告)日：2019-01-31

申请号：US16150637

申请日：2018-10-03

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Ritu Chaba ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: H01L27/11 ,  G11C8/14 ,  G11C11/418 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L21/768 ,  H01L21/3213 ,  G11C11/419 ,  G11C8/16

Abstract: An apparatus includes first means for routing current coupled to a bit cell. The apparatus includes third means for routing current. The third means for routing current includes a write word line coupled to the bit cell. The apparatus includes second means for routing current. The second means for routing current is between the first means for routing current and the third means for routing current. The second means for routing current includes two read word lines coupled to the bit cell.

公开(公告)号：US10175571B2

公开(公告)日：2019-01-08

申请号：US15182510

申请日：2016-06-14

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Hyeokjin Bruce Lim ,  Ohsang Kwon ,  Mickael Malabry ,  Jingwei Zhang ,  Raymond George Stephany ,  Haining Yang ,  Kern Rim ,  Stanley Seungchul Song ,  Mukul Gupta ,  Foua Vang

IPC: G06F17/50 ,  G03F1/70 ,  G03F7/20

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

公开(公告)号：US10141317B2

公开(公告)日：2018-11-27

申请号：US15347530

申请日：2016-11-09

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Ritu Chaba ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: H01L27/11 ,  G11C8/14 ,  G11C11/418 ,  H01L27/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  G11C8/16 ,  G11C11/419

Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

公开(公告)号：US10079293B2

公开(公告)日：2018-09-18

申请号：US15839050

申请日：2017-12-12

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

公开(公告)号：US10043796B2

公开(公告)日：2018-08-07

申请号：US15097142

申请日：2016-04-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Da Yang ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/06

Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

公开(公告)号：US10037795B2

公开(公告)日：2018-07-31

申请号：US14499149

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.

公开(公告)号：US20170278842A1

公开(公告)日：2017-09-28

申请号：US15081702

申请日：2016-03-25

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/06 ,  H01L29/66 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

Abstract: An integrated circuit includes a FinFET and a nanostructure FET. The integrated circuit includes a bulk substrate. The integrated circuit also includes a fin field effect transistor (FinFET) coupled to the bulk substrate. The FinFET includes a first source region, a first drain region, and a fin extending between the first source region and the first drain region. The integrated circuit also includes a nanostructure FET coupled to the bulk substrate. The nanostructure FET includes a second source region, a second drain region, and a stack of at least two nanostructures extending between the second source region and the second drain region.

公开(公告)号：US20170221884A1

公开(公告)日：2017-08-03

申请号：US15097142

申请日：2016-04-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Da Yang ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/0688 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/42392

Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.