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    Semiconductor device and method of making semiconductor device
    94.
    发明授权
    Semiconductor device and method of making semiconductor device 有权
    半导体器件及制造半导体器件的方法

    公开(公告)号：US08405226B2

    公开(公告)日：2013-03-26

    申请号：US13495195

    申请日：2012-06-13

    Applicant: John U. Knickerbocker ,  Chirag S. Patel

    Inventor： John U. Knickerbocker ,  Chirag S. Patel

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L23/5286 ,  H01L21/486 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: A method of fabricating a semiconductor device including forming a micro-chip comprising a thinned-wafer having one or more components fabricated thereon disposed between a carrier and a semiconductor chip, the micro-chip being electrically connected to the semiconductor chip under a higher consumption macro of the semiconductor chip and including a thickness which is less than a thickness of the semiconductor chip, forming an interconnect between the semiconductor chip and the carrier, forming an interconnect between the micro-chip and the semiconductor chip, and forming an interconnect between the micro-chip and the carrier. The micro-chip includes a thinned micro-chip having a thickness of less than 20 microns and the semiconductor chip includes plural semiconductor chips formed as a chip stack. The micro-chip includes a plurality of micro-chips formed on the plural semiconductor chips, such that the semiconductor device is a three-dimensional integrated circuit.

    Abstract translation: 一种制造半导体器件的方法，包括形成包括在其上制造的一个或多个部件的薄化晶片的微型芯片，所述薄片晶片设置在载体和半导体芯片之间，所述微芯片在较高功耗的宏观下电连接到所述半导体芯片 并且包括小于半导体芯片的厚度的厚度，在半导体芯片和载体之间形成互连，在微芯片和半导体芯片之间形成互连，并且在微型芯片和微型芯片之间形成互连 芯片和载体。 微芯片包括厚度小于20微米的薄化微芯片，半导体芯片包括形成为芯片堆叠的多个半导体芯片。 微芯片包括形成在多个半导体芯片上的多个微芯片，使得半导体器件是三维集成电路。

    Three-dimensional silicon interposer for low voltage low power systems
    96.
    发明授权
    Three-dimensional silicon interposer for low voltage low power systems 有权
    用于低压低功率系统的三维硅插入器

    公开(公告)号：US08344512B2

    公开(公告)日：2013-01-01

    申请号：US12544987

    申请日：2009-08-20

    Applicant: John U. Knickerbocker

    Inventor： John U. Knickerbocker

    IPC: H01L23/535

    CPC classification number: H01L21/486 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3025

    Abstract: Scalable silicon (Si) interposer configurations that support low voltage, low power operations are provided. In one aspect, a Si interposer is provided which includes a plurality of through-silicon vias (TSVs) within a first plane thereof adapted to serve as power, ground and signal interconnections throughout the first plane such that the TSVs that serve as the power and ground interconnections are greater in number and/or size than the TSVs that serve as the signal interconnections; and a plurality of lines within a second plane of the interposer in contact with one or more of the TSVs in the first plane, the second plane being adjacent to the first plane, adapted to serve as power, ground and signal interconnections throughout the second plane such that the lines that serve as the power and the ground interconnections are greater in number and/or size than the lines that serve as the signal interconnections.

    Abstract translation: 提供支持低电压，低功耗操作的可扩展硅（Si）插入器配置。 在一个方面，提供了一种Si插入器，其包括在其第一平面内的多个穿硅通孔（TSV），其适于在整个第一平面中用作功率，接地和信号互连，使得用作功率的TSV和 接地互连的数量和/或尺寸大于用作信号互连的TSV; 以及在所述插入器的第二平面内的与所述第一平面中的一个或多个TSV接触的多条线，所述第二平面与所述第一平面相邻，适于用作贯穿所述第二平面的功率，接地和信号互连 使得用作功率和接地互连的线路的数量和/或尺寸大于用作信号互连的线路。

    Structure and method for creating reliable deep via connections in a silicon carrier
    99.
    发明授权
    Structure and method for creating reliable deep via connections in a silicon carrier 有权
    用于在硅载体中创建可靠的深通孔连接的结构和方法

    公开(公告)号：US08080876B2

    公开(公告)日：2011-12-20

    申请号：US12147466

    申请日：2008-06-26

    Applicant: Paul S. Andry ,  John U. Knickerbocker ,  Michelle L. Steen ,  Cornelia K. Tsang

    Inventor： Paul S. Andry ,  John U. Knickerbocker ,  Michelle L. Steen ,  Cornelia K. Tsang

    IPC: H01L23/538

    CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.

    Abstract translation: 一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。 与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。 通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。

    INJECTION MOLDED SOLDERING PROCESS AND ARRANGEMENT FOR THREE-DIMENSIONAL STRUCTURES
    100.
    发明申请
    INJECTION MOLDED SOLDERING PROCESS AND ARRANGEMENT FOR THREE-DIMENSIONAL STRUCTURES 有权
    注射成型焊接工艺和三维结构布​​置

    公开(公告)号：US20100276813A1

    公开(公告)日：2010-11-04

    申请号：US12839214

    申请日：2010-07-19

    Applicant: Luc Belanger ,  David Danovitch ,  John U. Knickerbocker

    Inventor： Luc Belanger ,  David Danovitch ,  John U. Knickerbocker

    IPC: H01L23/488 ,  B23K31/02 ,  B23K1/20

    CPC classification number: H01L24/11 ,  H01L25/0657 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/0401

    Abstract: A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips. In accordance with a further aspect, it is possible to derive a unique design for an IMS mold structure, which contains cavities for forming the columnar fill of solder, and which also incorporates further cavities acting as cutouts for dies or the positioning of other electronic packages or modules.

    Abstract translation: 一种实现用于三维结构的注射成型焊接工艺的方法，特别是诸如针对三维半导体芯片堆叠的方法。 还提供了用于实现注射成型焊接（IMS）工艺的布置。 根据本发明的实施例，通过由IMS工艺形成的焊料柱的中间层，实现了半导体芯片层与基板的接合，而不是通过目前已知的引线键合堆叠，从而提供电气优点 由倒装芯片互连结构赋予。 在这方面，各种不同尺寸的焊料柱互连允许通过多个叠加层或诸如半导体芯片的半导体部件的堆叠阵列对衬底进行简单且可靠的连接。 根据另一方面，可以为IMS模具结构导出独特的设计，该模具结构包含用于形成焊料的柱状填充物的空腔，并且还包括用作模具的切口或其他电子封装的定位的另外的空腔 或模块。

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