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    Silicon based optical vias
    5.
    发明授权
    Silicon based optical vias 有权
    硅基光通孔

    公开(公告)号：US07352066B2

    公开(公告)日：2008-04-01

    申请号：US10675139

    申请日：2003-09-30

    申请人： Russell A. Budd ,  Punit P. Chiniwalla ,  Chirag S. Patel

    发明人： Russell A. Budd ,  Punit P. Chiniwalla ,  Chirag S. Patel

    IPC分类号： H01L23/48

    CPC分类号： G02B6/43 ,  H01L23/481 ,  H01L2924/0002 ,  H05K1/0274 ,  H01L2924/00

    摘要： Method of fabricating a semiconductor die with a microlens associated therewith. More particularly, a method for fabricating a vertical channel guide optical via through a silicon substrate wherein the optical via can contain lens elements, a discrete index gradient guiding pillar and other embodiments. Also disclosed are means for transferring, coupling and or focusing light from an electronic-optical device on the top of a semiconductor substrate through the substrate to a waveguiding medium below the substrate. The high alignment accuracies afforded by standard semiconductor fabrication processes are exploited so as to obviate the need for active alignment of the optical coupling or light guiding elements.

    摘要翻译： 制造具有与之相关联的微透镜的半导体管芯的方法。 更具体地，涉及一种通过硅衬底制造垂直沟道引导光通孔的方法，其中光通孔可以包含透镜元件，离散折射率梯度引导柱和其它实施例。 还公开了用于将来自半导体衬底顶部的电子光学器件的光通过衬底转移，耦合和聚焦到衬底下面的波导介质的装置。 利用由标准半导体制造工艺提供的高对准精度，以便消除对光学耦合或导光元件的主动对准的需要。

    Generating access point beacons at different power levels
    7.
    发明授权
    Generating access point beacons at different power levels 有权
    在不同的功率级别生成接入点信标

    公开(公告)号：US09119164B2

    公开(公告)日：2015-08-25

    申请号：US12542294

    申请日：2009-08-17

    申请人： Mehmet Yavuz ,  Sanjiv Nanda ,  Manoj M. Deshpande ,  Chirag S. Patel

    发明人： Mehmet Yavuz ,  Sanjiv Nanda ,  Manoj M. Deshpande ,  Chirag S. Patel

    IPC分类号： H04W4/00 ,  H04W52/32 ,  H04W52/24 ,  H04W52/28 ,  H04W84/04

    CPC分类号： H04W52/325 ,  H04W52/244 ,  H04W52/245 ,  H04W52/28 ,  H04W84/045

    摘要： An access point generates beacons at different power levels at different times to provide an acceptable tradeoff between coverage area associated with the beacons and outage experienced at nearby access terminals. For example, a femto access point may transmit beacons at a relatively low power for a relatively long period of time to reduce interference at nearby access terminals that are being served by a macro access point. The femto access point may then transmit beacons at a relatively high power for a relatively short period of time to enable nearby access terminals to receive the beacons. Also, a given transmit chain may be used to provide frequency hopping of high and low power beacons.

    摘要翻译： 接入点在不同时间产生不同功率电平的信标，以提供与信标相关联的覆盖区域和在附近接入终端处经历的中断之间的可接受的折中。 例如，毫微微接入点可以以相对较低的功率在相对长的时间段内发送信标，以减少正在由宏接入点服务的附近接入终端的干扰。 毫微微接入点然后可以在相对较短的时间段内以相对高的功率发送信标，以使附近的接入终端能够接收信标。 此外，给定的发射链可以用于提供高和低功率信标的跳频。

    Silicon based optical vias
    8.
    发明授权
    Silicon based optical vias 有权
    硅基光通孔

    公开(公告)号：US08755644B2

    公开(公告)日：2014-06-17

    申请号：US12080266

    申请日：2008-04-01

    申请人： Russell A. Budd ,  Punit P. Chiniwalla ,  Chirag S. Patel

    发明人： Russell A. Budd ,  Punit P. Chiniwalla ,  Chirag S. Patel

    IPC分类号： G02B6/12 ,  H01L21/00 ,  H01L23/48

    CPC分类号： G02B6/4206 ,  G02B6/4214 ,  H01L33/58 ,  H01S5/005 ,  H01S5/02248 ,  H01S5/02288 ,  H01S5/183

    摘要： Method of fabricating a semiconductor die with a microlens associated therewith. More particularly, a method for fabricating a vertical channel guide optical via through a silicon substrate wherein the optical via can contain lens elements, a discrete index gradient guiding pillar and other embodiments. Also disclosed are means for transferring, coupling and or focusing light from an electronic-optical device on the top of a semiconductor substrate through the substrate to a waveguiding medium below the substrate. The high alignment accuracies afforded by standard semiconductor fabrication processes are exploited so as to obviate the need for active alignment of the optical coupling or light guiding elements.

    摘要翻译： 制造具有与之相关联的微透镜的半导体管芯的方法。 更具体地，涉及一种通过硅衬底制造垂直沟道引导光通孔的方法，其中光通孔可以包含透镜元件，离散折射率梯度引导柱和其它实施例。 还公开了用于将来自半导体衬底顶部的电子光学器件的光通过衬底转移，耦合和聚焦到衬底下面的波导介质的装置。 利用由标准半导体制造工艺提供的高对准精度，以便消除对光学耦合或导光元件的主动对准的需要。

    Semiconductor device and method of making semiconductor device
    9.
    发明授权
    Semiconductor device and method of making semiconductor device 有权
    半导体器件及制造半导体器件的方法

    公开(公告)号：US08405226B2

    公开(公告)日：2013-03-26

    申请号：US13495195

    申请日：2012-06-13

    申请人： John U. Knickerbocker ,  Chirag S. Patel

    发明人： John U. Knickerbocker ,  Chirag S. Patel

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/5286 ,  H01L21/486 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor device including forming a micro-chip comprising a thinned-wafer having one or more components fabricated thereon disposed between a carrier and a semiconductor chip, the micro-chip being electrically connected to the semiconductor chip under a higher consumption macro of the semiconductor chip and including a thickness which is less than a thickness of the semiconductor chip, forming an interconnect between the semiconductor chip and the carrier, forming an interconnect between the micro-chip and the semiconductor chip, and forming an interconnect between the micro-chip and the carrier. The micro-chip includes a thinned micro-chip having a thickness of less than 20 microns and the semiconductor chip includes plural semiconductor chips formed as a chip stack. The micro-chip includes a plurality of micro-chips formed on the plural semiconductor chips, such that the semiconductor device is a three-dimensional integrated circuit.

    摘要翻译： 一种制造半导体器件的方法，包括形成包括在其上制造的一个或多个部件的薄化晶片的微型芯片，所述薄片晶片设置在载体和半导体芯片之间，所述微芯片在较高功耗的宏观下电连接到所述半导体芯片 并且包括小于半导体芯片的厚度的厚度，在半导体芯片和载体之间形成互连，在微芯片和半导体芯片之间形成互连，并且在微型芯片和微型芯片之间形成互连 芯片和载体。 微芯片包括厚度小于20微米的薄化微芯片，半导体芯片包括形成为芯片堆叠的多个半导体芯片。 微芯片包括形成在多个半导体芯片上的多个微芯片，使得半导体器件是三维集成电路。

    Chip system architecture for performance enhancement, power reduction and cost reduction
    10.
    发明授权
    Chip system architecture for performance enhancement, power reduction and cost reduction 有权
    芯片系统架构，用于性能提升，功耗降低和成本降低

    公开(公告)号：US07518225B2

    公开(公告)日：2009-04-14

    申请号：US11538567

    申请日：2006-10-04

    申请人： Philip G. Emma ,  John U. Knickerbocker ,  Chirag S. Patel

    发明人： Philip G. Emma ,  John U. Knickerbocker ,  Chirag S. Patel

    IPC分类号： H01L23/02

    CPC分类号： H01L25/0657 ,  H01L23/642 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

    摘要： A computer chip is structured to have at least one single-layered chip, at least one multi-layered chip stack, and a carrier package characterized by electrical interconnections of less than 100 microns diameter, wherein the single-layered chip and the multi-layered chip stack are each electrically coupled to the electrical interconnections of the carrier package, and the single-layered chip is communicatively coupled to the multi-layered chip stack through the carrier package so that an electrical signal propagates over a given distance between the single-layered chip and the multi-layered chip stack at substantially a speed of propagation for a single layer chip over the given distance. The single-layered chip can be a processor having multi-cores and the multi-layered chip stack can be a memory cache stack. Interconnect vias, having a density at least as great as 2500 interconnects/cm2 electrically couple the single-layered chip and the multi-layered chip stack to the carrier package.

    摘要翻译： 计算机芯片被构造成具有至少一个单层芯片，至少一个多层芯片堆叠和以小于100微米直径的电互连为特征的载体封装，其中单层芯片和多层芯片 芯片堆叠都电耦合到载体封装的电互连，并且单层芯片通过载体封装通信地耦合到多层芯片堆叠，使得电信号在单层之间传递给定距离 芯片和多层芯片堆栈，在给定距离内的单层芯片基本上是传播速度。 单层芯片可以是具有多核的处理器，并且多层芯片堆栈可以是存储器高速缓存堆栈。 具有至少高达2500个互连/ cm2的密度的互连通孔将单层芯片和多层芯片堆叠电耦合到载体封装。