公开(公告)号：US09647119B1

公开(公告)日：2017-05-09

申请号：US15201929

申请日：2016-07-05

Applicant: International Business Machines Corporation

Inventor： Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/10 ,  H01L27/092

CPC classification number: H01L21/845 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/7849

Abstract: A method of making a semiconductor device includes forming a first silicon germanium layer on a substrate, the first silicon germanium layer forming a portion of a first transistor; forming a second silicon germanium layer on the substrate adjacent to the first silicon germanium layer, the second silicon germanium layer forming a portion of a second transistor and having a germanium content that is different than the first silicon germanium layer and a thickness that is substantially the same; growing by an epitaxial process a compressively strained silicon germanium layer on the first silicon germanium layer, and a tensile strained silicon germanium layer on the second silicon germanium layer; patterning a first fin in the compressively strained silicon germanium layer and the first silicon germanium layer; and patterning a second fin in the tensile strained silicon germanium layer and the second silicon germanium layer.

公开(公告)号：US09634028B2

公开(公告)日：2017-04-25

申请号：US14929307

申请日：2015-10-31

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Pranita Kerber ,  Alexander Reznicek ,  Joshua M. Rubin

IPC: H01L29/00 ,  H01L27/12 ,  H01L21/84 ,  H01L29/45 ,  H01L29/66 ,  H01L21/285 ,  H01L21/324 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L29/08 ,  H01L29/06 ,  H01L21/283

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/845 ,  H01L23/485 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66795

Abstract: FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance.Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal.

公开(公告)号：US20170098646A1

公开(公告)日：2017-04-06

申请号：US14873859

申请日：2015-10-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kerber ,  Balasubramanian Pranatharthiharan ,  Ghavam G. Shahidi

IPC: H01L27/02

CPC classification number: H01L27/0292 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0266 ,  H01L29/0653

Abstract: A device having an electrostatic discharge structure includes a bulk substrate having a first dopant conductivity, first wells formed adjacent to a surface of the bulk substrate, including a second dopant conductivity, and second wells formed adjacent to the surface of the bulk substrate within the first wells, including the first dopant conductivity. A supply bus is formed in one of the first wells outside the second well. A ground bus has a first portion formed in another first well outside the second well, and a second portion is formed inside the second well such that a charge input to the second wells is dissipated without accumulating in the bulk substrate.

公开(公告)号：US20170069718A1

公开(公告)日：2017-03-09

申请号：US15353418

申请日：2016-11-16

Applicant: International Business Machines Corporation

Inventor： Jie Deng ,  Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/1054 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The at least one semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region is a dual channel region including a buried channel portion and a surface channel portion that completely surrounds the buried channel.

公开(公告)号：US20170062589A1

公开(公告)日：2017-03-02

申请号：US14953481

申请日：2015-11-30

Applicant: International Business Machines Corporation

Inventor： Jie Deng ,  Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/167 ,  H01L29/165

CPC classification number: H01L29/1054 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The at least one semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region is a dual channel region including a buried channel portion and a surface channel portion that completely surrounds the buried channel.

Abstract translation: 半导体器件包括在衬底的上表面上的至少一个半导体鳍片。 所述至少一个半导体鳍片包括介于相对的源极/漏极区域之间的沟道区域。 栅极堆叠在衬底的上表面上，并且仅包围沟道区域的侧壁和上表面。 通道区域是包括掩埋通道部分和完全围绕埋入通道的表面通道部分的双通道区域。

公开(公告)号：US09553166B1

公开(公告)日：2017-01-24

申请号：US14841033

申请日：2015-08-31

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Pranita Kerber ,  Effendi Leobandung ,  Amlan Majumdar ,  Renee T. Mo ,  Yanning Sun

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/311 ,  H01L21/225

CPC classification number: H01L29/7835 ,  H01L21/2258 ,  H01L21/31105 ,  H01L21/31116 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/32 ,  H01L29/66462 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material.

Abstract translation: 提供了包含高迁移率半导体沟道材料即III-V族半导体材料的半导体结构以及位于高迁移率半导体沟道材料的侧壁上的非对称源/漏区。 不对称的源极/漏极区域有助于改善所得器件的性能。 源极区域包含源极侧外延掺杂半导体材料，而漏极区域包含漏极侧外延掺杂半导体材料和高迁移率半导体沟道材料的下面部分。

公开(公告)号：US20160343734A1

公开(公告)日：2016-11-24

申请号：US14718500

申请日：2015-05-21

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Pranita Kerber ,  Alexander Reznicek ,  Joshua M. Rubin

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/66 ,  H01L21/285 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L29/08 ,  H01L21/84 ,  H01L21/324

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/845 ,  H01L23/485 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66795

Abstract: FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance. Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal.

Abstract translation: 提供FinFET器件，其中电流路径被最小化，并且在通道载体到达金属触点之前主要限于间隔区域。 源极/漏极区域中的鳍片被金属化以增加接触面积并降低接触电阻。 源极/漏极外延后的源极/漏极区域中选择性去除半导体鳍片有助于金属化鳍片的更换。 在源极/漏极外延之后形成的间隔物在半导体鳍片去除期间防止了延伸/沟道区域的蚀刻。

公开(公告)号：US20160293428A1

公开(公告)日：2016-10-06

申请号：US15183034

申请日：2016-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Keith E. Fogel ,  Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek

IPC: H01L21/285 ,  H01L29/161 ,  H01L29/16 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L23/535 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/41791 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed.

公开(公告)号：US09443940B1

公开(公告)日：2016-09-13

申请号：US14680328

申请日：2015-04-07

Applicant: International Business Machines Corporation

Inventor： Keith E. Fogel ,  Judson R. Holt ,  Pranita Kerber ,  Alexander Reznicek

IPC: H01L21/20 ,  H01L29/32 ,  H01L29/10 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/32 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66795

Abstract: A structure and method for fabricating a heteroepitaxially grown lattice-mismatched semiconductor layer with a lower defect density is disclosed. A first semiconductor layer is epitaxially grown on an upper surface of a lattice mismatched crystalline substrate in a lower trench using a first ART deposition process. The structure is then rotated 90° along a horizontal plane and a second semiconductor layer is epitaxially grown on an upper surface of the first semiconductor layer in an upper trench using a second ART deposition process. This results in an upper portion of the second semiconductor layer being substantially free of epitaxy defects.

Abstract translation: 公开了一种用于制造具有较低缺陷密度的异质外延生长晶格不匹配半导体层的结构和方法。 使用第一ART沉积工艺，在下沟槽中的晶格失配晶体衬底的上表面上外延生长第一半导体层。 然后将结构沿着水平面旋转90°，并且使用第二ART沉积工艺在上沟槽中在第一半导体层的上表面上外延生长第二半导体层。 这导致第二半导体层的上部基本上没有外延缺陷。

公开(公告)号：US09443873B1

公开(公告)日：2016-09-13

申请号：US14967526

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L21/845 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/7849

Abstract: A method of making a semiconductor device includes forming a first silicon germanium layer on a substrate, the first silicon germanium layer forming a portion of a first transistor; forming a second silicon germanium layer on the substrate adjacent to the first silicon germanium layer, the second silicon germanium layer forming a portion of a second transistor and having a germanium content that is different than the first silicon germanium layer and a thickness that is substantially the same; growing by an epitaxial process a compressively strained silicon germanium layer on the first silicon germanium layer, and a tensile strained silicon germanium layer on the second silicon germanium layer; patterning a first fin in the compressively strained silicon germanium layer and the first silicon germanium layer; and patterning a second fin in the tensile strained silicon germanium layer and the second silicon germanium layer.

Abstract translation: 制造半导体器件的方法包括在衬底上形成第一硅锗层，所述第一硅锗层形成第一晶体管的一部分; 在与第一硅锗层相邻的衬底上形成第二硅锗层，形成第二晶体管的一部分并具有不同于第一硅锗层的锗含量的第二硅锗层和基本上为 相同; 通过外延工艺生长在第一硅锗层上的压缩应变硅锗层和在第二硅锗层上的拉伸应变硅锗层; 图案化压缩应变硅锗层和第一硅锗层中的第一鳍; 以及在拉伸应变硅锗层和第二硅锗层中构图第二鳍片。