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    Memory system and method
    2.
    发明授权
    Memory system and method 有权

    公开(公告)号：US12130746B2

    公开(公告)日：2024-10-29

    申请号：US17898307

    申请日：2022-08-29

    申请人： KIOXIA CORPORATION

    发明人： Takahiro Kurita ,  Shinichi Kanno

    IPC分类号： G06F12/10 ,  G06F3/06

    CPC分类号： G06F12/10 ,  G06F3/0638 ,  G06F3/0679

    摘要： A memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory based on an address conversion table. The controller is configured to generate first address mapping information indicating a first logical address range and a first physical address range, and then second address mapping information indicating a second logical address range and a second physical address range, determine whether the first and second logical address ranges are continuous and the first and second physical address ranges are continuous, upon determining non-continuity of the logical or physical address ranges, update the address conversion table based on the first address mapping information, and upon determining continuity of the logical and physical address ranges, generate integrated address mapping information using the first and second address mapping information and update the address conversion table based on the integrated address mapping information.

    Method for determining physical address and chip system
    5.
    发明授权
    Method for determining physical address and chip system 有权

    公开(公告)号：US12086071B2

    公开(公告)日：2024-09-10

    申请号：US18042974

    申请日：2021-08-04

    申请人： Huawei Technologies Co., Ltd.

    发明人： Kailong Li ,  Hui Liang

    IPC分类号： G06F12/10

    CPC分类号： G06F12/10 ,  G06F2212/65

    摘要： A method includes: when a first virtual address of a first virtual address space is obtained, determining a first entry index address corresponding to the first virtual address; and determining, from a first page table based on the first entry index address, a first target physical address corresponding to the first virtual address. A second entry index address corresponding to a start virtual address of the first virtual address space is greater than or equal to a base address of the first page table, and is less than a sum of the base address of the first page table and a quotient of dividing the start virtual address by a size of a second virtual address space.

    DUAL ADDRESS ENCODING FOR LOGICAL-TO-PHYSICAL MAPPING
    6.
    发明公开
    DUAL ADDRESS ENCODING FOR LOGICAL-TO-PHYSICAL MAPPING 审中-公开

    公开(公告)号：US20240296125A1

    公开(公告)日：2024-09-05

    申请号：US18662743

    申请日：2024-05-13

    申请人： Lodestar Licensing Group LLC

    发明人： Giuseppe Cariello ,  Jonathan S. Parry

    IPC分类号： G06F12/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

    CPC分类号： G06F12/10 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G06F2212/657 ,  G11C2216/14

    摘要： Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.

    Data integrity protection of SSDs utilizing streams
    8.
    发明授权
    Data integrity protection of SSDs utilizing streams 有权

    公开(公告)号：US12079504B2

    公开(公告)日：2024-09-03

    申请号：US18093734

    申请日：2023-01-05

    申请人： Western Digital Technologies, Inc.

    发明人： Daniel L. Helmick ,  Peter Grayson

    IPC分类号： G06F3/06 ,  G06F1/30 ,  G06F12/0804 ,  G06F12/10

    CPC分类号： G06F3/065 ,  G06F1/30 ,  G06F3/0604 ,  G06F3/068 ,  G06F12/0804 ,  G06F12/10 ,  G06F2212/1032 ,  G06F2212/657

    摘要： The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. When a write command is received to write data to a stream, change log data is generated and stored in the RAM1, the previous delta data for the stream is copied from the RAM2 to the RAM1 to be updated with the change log data, and the updated delta data is copied to the RAM2. The delta data stored in the RAM2 is copied to the storage unit periodically. The controller tracks which delta data has been copied to the RAM2 and to the storage unit. During a power failure, the delta data and the change log data are copied from the RAM1 or the RAM2 to the storage unit.

    Efficient address translation
    10.
    发明授权
    Efficient address translation 有权

    公开(公告)号：US12079138B2

    公开(公告)日：2024-09-03

    申请号：US17892879

    申请日：2022-08-22

    申请人： Intel Corporation

    发明人： Jianhui Li ,  Yong Wu ,  Yihua Jin ,  Xueliang Zhong ,  Xiao Lin

    IPC分类号： G06F12/10 ,  G06F9/30 ,  G06F9/355 ,  G06F9/455

    CPC分类号： G06F12/10 ,  G06F9/30174 ,  G06F9/355 ,  G06F9/45554 ,  G06F9/45558 ,  G06F2009/45583

    摘要： An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.