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公开(公告)号：US12217924B2
公开(公告)日：2025-02-04
申请号：US17834944
申请日：2022-06-08
Inventor： Yu-Wei Ting , Kuo-Pin Chang , Hung-Ju Li , Kuo-Ching Huang
Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a heater element on the semiconductor substrate, the heater element configured to generate heat in response to a current flowing therethrough. The semiconductor device also includes a conductor material having a programmable conductivity, and an insulator layer between the heater element and the conductor material, where the conductor material is configured to be programmed by applying one or more voltage differences to one or more of the heater element and the conductor material, and where a capacitance between the conductor material and the heater element is configured to be controlled by the voltage differences such that the capacitance is lower while the conductor material is being programmed than while the conductor material is not being programmed.
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公开(公告)号：US20240389349A1
公开(公告)日：2024-11-21
申请号：US18786231
申请日：2024-07-26
Inventor： Wei Ting Hsieh , Kuen-Yi Chen , Yi-Hsuan Chen , Yu-Wei Ting , Yi Ching Ong , Kuo-Ching Huang
Abstract: A semiconductor structure according to the present disclosure includes a conductive feature in a top portion of a substrate, a bottom electrode layer over and in electrical coupling with the conductive feature, an insulator layer over the bottom electrode layer, a semiconductor layer over the insulator layer, a ferroelectric layer over the semiconductor layer, and a top electrode layer over the ferroelectric layer. The semiconductor layer includes a plurality of portions with different thicknesses.
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公开(公告)号：US20240379656A1
公开(公告)日：2024-11-14
申请号：US18780581
申请日：2024-07-23
Inventor： Yi Ching Ong , Kuen-Yi Chen , Yi-Hsuan Chen , Kuo-Ching Huang , Harry-Hak-Lay Chuang
IPC: H01L27/06 , H01L23/495 , H01L23/538
Abstract: The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.
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公开(公告)号：US20230402241A1
公开(公告)日：2023-12-14
申请号：US17834944
申请日：2022-06-08
Inventor： Yu-Wei Ting , Kuo-Pin Chang , Hung-Ju Li , Kuo-Ching Huang
Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a heater element on the semiconductor substrate, the heater element configured to generate heat in response to a current flowing therethrough. The semiconductor device also includes a conductor material having a programmable conductivity, and an insulator layer between the heater element and the conductor material, where the conductor material is configured to be programmed by applying one or more voltage differences to one or more of the heater element and the conductor material, and where a capacitance between the conductor material and the heater element is configured to be controlled by the voltage differences such that the capacitance is lower while the conductor material is being programmed than while the conductor material is not being programmed.
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公开(公告)号：US20230389324A1
公开(公告)日：2023-11-30
申请号：US18181229
申请日：2023-03-09
Inventor： Yi-Hsuan Chen , Kuen-Yi Chen , Yi Ching Ong , Yu-Wei Ting , Kuo-Chi Tu , Kuo-Ching Huang , Harry-Hak-Lay Chuang
IPC: H10B51/20 , H01L21/28 , H01L29/51 , H01L29/66 , H01L29/78 , H01L23/522 , H01L23/528
CPC classification number: H10B51/20 , H01L29/40111 , H01L29/516 , H01L29/6684 , H01L29/78391 , H01L23/5226 , H01L23/5283
Abstract: A method of forming a memory device according to the present disclosure includes forming a trench in a first substrate of a first wafer, depositing a data-storage element in the trench, performing a thermal treatment to the first wafer to improve a crystallization in the data-storage element, forming a first redistribution layer over the first substrate, forming a transistor in a second substrate of a second wafer, forming a second redistribution layer over the second substrate, and bonding the first wafer with the second wafer after the performing of the thermal treatment. The data-storage element is electrically coupled to the transistor through the first and second redistribution layers.
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Patent Agency Ranking
公开(公告)号：US20150318292A1
公开(公告)日：2015-11-05
申请号：US14798743
申请日：2015-07-14
Inventor： Yu-Wei Ting , Kuo-Ching Huang , Chih-Yang Pai
IPC: H01L27/115 , H01L29/423
CPC classification number: H01L27/11521 , H01L29/40117 , H01L29/42324 , H01L29/42344 , H01L29/42356 , H01L29/66833 , H01L29/792
Abstract: The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.
Abstract translation: 本公开描述了形成存储器件的方法。 该方法包括接收晶片衬底，在晶片衬底上形成多晶堆叠图案，执行离子注入工艺以在晶片衬底中形成源极和漏极，在限定的多晶堆叠图案中形成存储栅极和控制栅极， 以及在所述控制多晶堆叠图案中形成控制栅极。 形成存储器栅极还包括执行存储器栅极凹槽以将存储栅极埋入氧化物层中。
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公开(公告)号：US08953370B2
公开(公告)日：2015-02-10
申请号：US13773366
申请日：2013-02-21
Inventor： Yu-Wei Ting , Kuo-Ching Huang , Chun-Yang Tsai
CPC classification number: G11C7/02 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/32 , G11C2213/79 , G11C2213/82
Abstract: A memory cell with a decoupled read/write path includes a switch comprising a first terminal connected to a first line and a second terminal connected to a second line, a resistive switching device connected between a gate of the switch and a third line, and a conductive path between the gate of the switch and the second line.
Abstract translation: 具有解耦读/写路径的存储单元包括开关，其包括连接到第一线路的第一端子和连接到第二线路的第二端子，连接在开关的栅极和第三线路之间的电阻式开关装置，以及 开关栅极与第二线路之间的导电路径。
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8.发明授权Resistive switching random access memory structure and method to recreate filament and recover resistance window 有权电阻式开关随机存取存储器结构和重建灯丝并恢复电阻窗的方法公开(公告)号：US08869436B2
公开(公告)日：2014-10-28
申请号：US13779030
申请日：2013-02-27
Inventor： Chun-Yang Tsai , Yu-Wei Ting , Kuo-Ching Huang
CPC classification number: G11C13/0004 , G11C11/5685 , G11C13/0007 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/79
Abstract: The present disclosure provides one embodiment of a method for operating a resistive random access memory (RRAM) cell. The method includes performing a forming operation to the RRAM cell with a forming voltage; performing a number of set/reset operation cycles to the RRAM cell; and performing a recreating process to the RRAM cell to recover RRAM resistance by applying a recreating voltage. Each of the number of set/reset operation cycles includes a set operation with a set voltage. The recreating voltage is greater than the set voltage.
Abstract translation: 本公开提供了用于操作电阻随机存取存储器（RRAM）单元的方法的一个实施例。 该方法包括：以成形电压对RRAM单元执行成形操作; 对RRAM单元执行多个置位/复位操作周期; 并且通过应用重建电压对RRAM单元执行重新创建过程以恢复RRAM电阻。 多个设定/复位操作周期中的每一个包括具有设定电压的设定操作。 重建电压大于设定电压。
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9.发明申请Resistive Switching Random Access Memory Structure and Method To Recreate Filament and Recover Resistance Window 有权电阻式切换随机存取存储器结构和重建灯丝和恢复电阻窗的方法公开(公告)号：US20140241034A1
公开(公告)日：2014-08-28
申请号：US13779030
申请日：2013-02-27
Inventor： Chun-Yang Tsai , Yu-Wei Ting , Kuo-Ching Huang
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C11/5685 , G11C13/0007 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/79
Abstract: The present disclosure provides one embodiment of a method for operating a resistive random access memory (RRAM) cell. The method includes performing a forming operation to the RRAM cell with a forming voltage; performing a number of set/reset operation cycles to the RRAM cell; and performing a recreating process to the RRAM cell to recover RRAM resistance by applying a recreating voltage. Each of the number of set/reset operation cycles includes a set operation with a set voltage. The recreating voltage is greater than the set voltage.
Abstract translation: 本公开提供了用于操作电阻随机存取存储器（RRAM）单元的方法的一个实施例。 该方法包括：以成形电压对RRAM单元执行成形操作; 对RRAM单元执行多个置位/复位操作周期; 并且通过应用重建电压对RRAM单元执行重新创建过程以恢复RRAM电阻。 多个设定/复位操作周期中的每一个包括具有设定电压的设定操作。 重建电压大于设定电压。
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公开(公告)号：US20240057343A1
公开(公告)日：2024-02-15
申请号：US17819244
申请日：2022-08-11
Inventor： Kuen-Yi Chen , Yu-Sheng Chen , Yi Ching Ong , Kuo-Ching Huang
IPC: H01L27/11507
CPC classification number: H01L27/11507
Abstract: Provided are ferroelectric tunnel junction (FTJ) structures, memory devices, and methods for fabricating such structures and devices. An FTJ structure includes a first electrode, a ferroelectric material layer, and a catalytic metal layer in contact with the ferroelectric material layer.
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