公开(公告)号：US20170213781A1

公开(公告)日：2017-07-27

申请号：US15003238

申请日：2016-01-21

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@Eugene Lee ,  Chong Han Lim ,  You Chye How

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49537 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4839 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49589 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated circuit (IC) package includes a first leadframe having a top surface and a bottom surface. An IC die has an active side coupled to the first leadframe bottom surface and has a back side. A second leadframe has a top surface and a bottom surface. The back side of said IC chip is coupled to the top surface of the second leadframe.

公开(公告)号：US20160071743A1

公开(公告)日：2016-03-10

申请号：US14941865

申请日：2015-11-16

Applicant: Texas Instruments Incorporated

Inventor： You Chye How ,  Maria Christina Bernardo Violante

IPC: H01L21/48 ,  H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L21/4821 ,  H01L21/4828 ,  H01L21/565 ,  H01L21/6836 ,  H01L23/00 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/94 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/27003 ,  H01L2224/27436 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1515 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2924/0781

Abstract: A method of making an integrated circuit package. A leadframe having a die attach paddle surrounded by lead portions is formed. Middle channels underlying in said die attach paddle portion in a region thereof adapted to receive a first die are formed

Abstract translation: 一种制造集成电路封装的方法。 形成具有由引线部分包围的管芯附着焊盘的引线框架。 形成在适于接收第一管芯的区域中的所述管芯附接叶片部分中的下部通道

公开(公告)号：US20150262920A1

公开(公告)日：2015-09-17

申请号：US14215605

申请日：2014-03-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： You Chye How ,  Huay Yann Tay

IPC: H01L23/495 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L24/13 ,  H01L21/4825 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49589 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02205 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/11618 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13078 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13616 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/1607 ,  H01L2224/16113 ,  H01L2224/16245 ,  H01L2224/16503 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83815 ,  H01L2224/92225 ,  H01L2924/01327 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An integrated circuit (“IC”) package including at least one IC die having a first side with at least two adjacent bump pads thereon and a second side opposite the first side; a first substrate having a first side with a plurality of electrical contact surfaces thereon; and a plurality of copper pillars, each having a first end attached to one of the adjacent bump pads and a second end attached to one of the electrical contact surfaces.

Abstract translation: 一种集成电路（“IC”）封装，其包括至少一个具有第一侧的IC管芯，其上具有至少两个相邻的凸点焊盘和与第一侧相对的第二侧; 第一基板，其上具有多个电接触表面的第一侧; 以及多个铜柱，每个铜柱具有附接到相邻凸块之一的第一端和连接到电接触表面之一的第二端。

公开(公告)号：US20150035130A1

公开(公告)日：2015-02-05

申请号：US13954916

申请日：2013-07-30

Applicant: Texas Instruments Incorporated

Inventor： You Chye How

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L23/3107 ,  H01L23/315 ,  H01L2924/0002 ,  H01L2924/16235 ,  H01L2924/00

Abstract: A packaged semiconductor device has a semiconductor substrate with circuitry formed thereon. A shield plate is mounted over a designated region of the substrate and separated from the semiconductor substrate by a separator, such that the shield plate is separated from the designated region of the substrate by a distance. Mold compound encapsulates the semiconductor substrate and the shield plate, but is prevented from touching the designated region of the substrate by the shield plate.

Abstract translation: 封装的半导体器件具有形成在其上的电路的半导体衬底。 屏蔽板安装在基板的指定区域上，并通过隔板与半导体基板分离，使得屏蔽板与基板的指定区域分开一段距离。 模具化合物封装半导体衬底和屏蔽板，但是防止了屏蔽板接触衬底的指定区域。

公开(公告)号：US11328984B2

公开(公告)日：2022-05-10

申请号：US15858948

申请日：2017-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： You Chye How ,  Huay Yann Tay ,  Franklin Santos Marcelino

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: Multi-die integrated circuit packages and methods of manufacturing the same are disclosed. An example integrated circuit package includes a first leadframe, a first die on a first side of the first leadframe, and a second die on a second side of the first leadframe opposite the first side. The example integrated circuit package further includes external second leadframe separate from the first leadframe.

公开(公告)号：US20190206772A1

公开(公告)日：2019-07-04

申请号：US15858948

申请日：2017-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： You Chye How ,  Huay Yann Tay ,  Franklin Santos Marcelino

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/49575 ,  H01L21/4839 ,  H01L21/4842 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49805 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/32141 ,  H01L2224/48091 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49109 ,  H01L2224/73265

Abstract: Multi-die integrated circuit packages and methods of manufacturing the same are disclosed. An example integrated circuit package includes a first leadframe, a first die on a first side of the first leadframe, and a second die on a second side of the first leadframe opposite the first side. The example integrated circuit package further includes external second leadframe separate from the first leadframe.

公开(公告)号：US20180261469A1

公开(公告)日：2018-09-13

申请号：US15955435

申请日：2018-04-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： You Chye How

IPC: H01L21/56 ,  H01L21/78 ,  H01L25/00 ,  H01L25/16 ,  H01L21/48 ,  H01L21/683

Abstract: Disclosed examples include a method of making a semiconductor die package comprising arranging at least one preformed die attach pad and at least two preformed leads on a lead frame carrier in a predetermined configuration to form a lead frame, attaching a semiconductor die to the at least one preformed die attach pad, wire bonding the semiconductor die to the at least two preformed leads, forming a molding structure including at least part of the semiconductor die and the at least two preformed leads, and removing the molding structure from the lead frame carrier.

公开(公告)号：US20150243639A1

公开(公告)日：2015-08-27

申请号：US14192402

申请日：2014-02-27

Applicant: Texas Instruments Incorporated

Inventor： You Chye How ,  Siew Kee Lee ,  Huay Yann Tay

IPC: H01L25/16 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/532 ,  H01L21/768 ,  H01L21/56 ,  H01L23/495 ,  H01L23/48

CPC classification number: H01L25/165 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49541 ,  H01L23/53214 ,  H01L23/53228 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/81801 ,  H01L2224/9212 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/19106 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00014

Abstract: A method for packaging integrated circuit die such that each package includes die with integrated passive components mounted to either the back surface, the active surface or both the back and active surfaces of the die.

Abstract translation: 一种用于封装集成电路管芯的方法，使得每个封装包括具有安装到管芯的背表面，活性表面或后表面和有源表面的集成无源元件的管芯。

公开(公告)号：US11837518B2

公开(公告)日：2023-12-05

申请号：US17003382

申请日：2020-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Todd Wyant ,  Matthew John Sherbin ,  Christopher Daniel Manack ,  Patrick Francis Thompson ,  You Chye How

IPC: H01L23/31 ,  H01L23/552 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L23/3185 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/552 ,  H01L21/6836 ,  H01L2221/68336

Abstract: In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.

公开(公告)号：US10804114B2

公开(公告)日：2020-10-13

申请号：US15138298

申请日：2016-04-26

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  You Chye How

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00

Abstract: A method for forming a multilevel leadframe for an integrated circuit is provided. A conductive sheet is etched from one side to form a thinner region within a frame region for leads lines and bond pads. The conductive sheet is etched to form a plurality of bond pads in a first level of the thinner region arranged in at least a first row and a second row. Each bond pad has a pad width and is separated from an adjacent bond pad by a bond pad clearance distance. The conductive sheet is etched from an opposite side to form a plurality of lead lines in a second level of the thinner region having a line width and is separated from an adjacent lead line by at least a lead line clearance distance. Each bond pad of the second plurality of bond pads is connected to one of the plurality of lead lines on the second level that is routed between adjacent bond pads in the first row, so that the lead lines are routed on a different level from the bond pads.