公开(公告)号：US11830911B2

公开(公告)日：2023-11-28

申请号：US18162892

申请日：2023-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Sun ,  Dae Won Ha ,  Dong Hoon Hwang ,  Jong Hwa Baek ,  Jong Min Jeon ,  Seung Mo Ha ,  Kwang Yong Yang ,  Jae Young Park ,  Young Su Chung

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/417 ,  H10B10/00

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/41791 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.

公开(公告)号：US11830775B2

公开(公告)日：2023-11-28

申请号：US17698487

申请日：2022-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Sun ,  Myeong-Cheol Kim ,  Kyoung-Sub Shin

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  G06F7/505 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  G06F30/39 ,  G06F30/398 ,  G06F119/12 ,  G06F117/12

CPC classification number: H01L21/823807 ,  G06F7/505 ,  G06F30/39 ,  G06F30/398 ,  H01L21/308 ,  H01L21/30608 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  G06F2117/12 ,  G06F2119/12

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US10529801B2

公开(公告)日：2020-01-07

申请号：US15933827

申请日：2018-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Chul Sun ,  Dae Won Ha ,  Dong Hoon Hwang ,  Jong Hwa Baek ,  Jong Min Jeon ,  Seung Mo Ha ,  Kwang Yong Yang ,  Jae Young Park ,  Young Su Chung

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L27/11

Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.

公开(公告)号：US20200211907A1

公开(公告)日：2020-07-02

申请号：US16810937

申请日：2020-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Sun ,  Myeong-Cheol KIM ,  Kyoung-Sub SHIN

IPC: H01L21/8238 ,  G06F7/505 ,  H01L23/535 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/092 ,  H01L21/308 ,  H01L21/306 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  G06F30/398 ,  G06F30/39

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US10014219B2

公开(公告)日：2018-07-03

申请号：US15441594

申请日：2017-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Sun ,  Byung-Gook Park

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/786 ,  H01L29/78 ,  H01L27/088 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/823412 ,  B82Y99/00 ,  H01L21/02532 ,  H01L21/02647 ,  H01L21/3065 ,  H01L27/088 ,  H01L27/1222 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/772 ,  H01L29/7843 ,  H01L29/78651 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

Abstract: A semiconductor device includes a structure on a substrate and a plurality of gate-all-around devices on the structure. The structure includes a plurality of sacrificial layers and a plurality of active layers alternately stacked on one another. The sacrificial layers have different widths and the active layers have different widths to form multiple stepped layers on the substrate. The gate-all-around devices are on respective ones the multiple stepped layers.

公开(公告)号：US09583583B2

公开(公告)日：2017-02-28

申请号：US14969025

申请日：2015-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Seoul National University R&DB Foundation

Inventor： Min-Chul Sun ,  Byung-Gook Park

IPC: H01L31/072 ,  H01L29/423 ,  H01L29/06 ,  H01L27/088 ,  H01L29/772 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/12 ,  B82Y99/00

CPC classification number: H01L21/823412 ,  B82Y99/00 ,  H01L21/02532 ,  H01L21/02647 ,  H01L21/3065 ,  H01L27/088 ,  H01L27/1222 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/772 ,  H01L29/7843 ,  H01L29/78651 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

Abstract translation: 半导体器件具有形成在基板上的各个区域中的栅极全绕器件。 全门设备具有不同级别的纳米线。 第一区域中的栅极全周围器件的阈值电压基于相邻第二区域中的有源层的厚度。 第二区域中的有源层可以处于与第一区域中的纳米线基本相同的水平。 因此，第一区域中的纳米线可以具有基于第二区域中的有源层的厚度的厚度，或者厚度可以不同。 当包括多于一个活性层时，不同区域中的纳米线可以设置在不同的高度和/或可以具有不同的厚度。

公开(公告)号：US11302585B2

公开(公告)日：2022-04-12

申请号：US16810937

申请日：2020-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Sun ,  Myeong-Cheol Kim ,  Kyoung-Sub Shin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  G06F7/505 ,  G06F30/39 ,  G06F30/398 ,  G06F119/12 ,  G06F117/12

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US09634093B2

公开(公告)日：2017-04-25

申请号：US15151747

申请日：2016-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Sun ,  Byung-Gook Park

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.

公开(公告)号：US09461054B2

公开(公告)日：2016-10-04

申请号：US14789433

申请日：2015-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Chul Sun ,  Byung-Gook Park

IPC: H01L27/11 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/7827

Abstract: A semiconductor device comprises a substrate extending in a horizontal direction and a vertical transistor on the substrate. The vertical transistor comprises: a first diffusion region on the substrate; a channel region on the first diffusion region and extending in a vertical direction relative to the horizontal direction of the extension of the substrate; a second diffusion region on the channel region; and a gate electrode at a sidewall of, and insulated from, the channel region. A horizontal transistor is positioned on the substrate, the horizontal transistor comprising: a first diffusion region and a second diffusion region on the substrate and spaced apart from each other; a channel region on the substrate between the first diffusion region and the second diffusion region; and a gate electrode on the channel region and isolated from the channel region. A portion of a gate electrode of the vertical transistor and a portion of the gate electrode of the horizontal transistor are at a same vertical position in the vertical direction relative to the substrate.

Abstract translation: 半导体器件包括在水平方向上延伸的衬底和在衬底上的垂直晶体管。 所述垂直晶体管包括：所述基板上的第一扩散区域; 在所述第一扩散区域上的相对于所述基板的延伸部的水平方向在垂直方向上延伸的沟道区域; 沟道区上的第二扩散区; 以及在沟道区的侧壁处和绝缘的栅电极。 水平晶体管位于衬底上，水平晶体管包括：在衬底上的第一扩散区和第二扩散区，彼此间隔开; 在所述第一扩散区域和所述第二扩散区域之间的衬底上的沟道区域; 以及沟道区上的栅极，并与沟道区分离。 垂直晶体管的栅电极的一部分和水平晶体管的栅电极的一部分在垂直方向上相对于衬底处于相同的垂直位置。

公开(公告)号：US09343549B2

公开(公告)日：2016-05-17

申请号：US14049479

申请日：2013-10-09

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Seoul National University R&DB Foundation

Inventor： Min-Chul Sun ,  Byung-Gook Park

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.

Abstract translation: 一种制造半导体器件的方法包括：在衬底上形成第一掩模，通过使用第一掩模执行衬底的第一蚀刻形成鳍的第一侧壁，在衬底上形成第二掩模，第二掩模不同 并且通过使用所述第二掩模对所述基板进行第二蚀刻来形成所述翅片的第二侧壁。