公开(公告)号：US12009398B2

公开(公告)日：2024-06-11

申请号：US17932851

申请日：2022-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Tae-Yeol Kim ,  Jae-Jik Baek

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/40

CPC classification number: H01L29/41775 ,  H01L23/5226 ,  H01L29/401

Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

公开(公告)号：US09136135B2

公开(公告)日：2015-09-15

申请号：US13944087

申请日：2013-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jik Baek ,  Ji-Hoon Cha ,  Bo-Un Yoon ,  Kwang-Wook Lee ,  Jeong-Nam Han

IPC: H01L21/306 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/30604 ,  H01L21/30608 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, and etching sides of the gate pattern using a first wet-etching process to form a first recess. The first wet-etching process includes using an etchant containing a first chemical substance including a hydroxyl functional group (—OH) and a second chemical substance capable of oxidizing the substrate. The concentration of the second chemical substance is 1.5 times or less the concentration of the first chemical substance.

Abstract translation: 制造半导体器件的方法包括在衬底上形成栅极图案，并且使用第一湿蚀刻工艺蚀刻栅极图案的侧面以形成第一凹部。 第一湿蚀刻工艺包括使用含有包含羟基官能团（-OH）的第一化学物质和能够氧化底物的第二化学物质的蚀刻剂。 第二化学物质的浓度为第一化学物质浓度的1.5倍以下。

公开(公告)号：US20240297232A1

公开(公告)日：2024-09-05

申请号：US18655409

申请日：2024-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Tae-Yeol Kim ,  Jae-Jik Baek

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/40

CPC classification number: H01L29/41775 ,  H01L23/5226 ,  H01L29/401

Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

公开(公告)号：US09972696B2

公开(公告)日：2018-05-15

申请号：US15229930

申请日：2016-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoyoung Kim ,  Sang Won Bae ,  Jae-Jik Baek ,  Wonsang Choi

IPC: H01L21/3213 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3205 ,  C09K13/00

CPC classification number: H01L29/66545 ,  C09K13/00 ,  H01L21/28017 ,  H01L21/28255 ,  H01L21/32055 ,  H01L21/32134 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: The present disclosure relates to an etchant, a method of making an etchant, an etching method and a method of fabricating a semiconductor device using the same. The etching method includes supplying an etchant on an etch-target layer to etch the etch-target layer in a wet etch manner. The etchant contains a basic compound and a sugar alcohol, and the basic compound contains ammonium hydroxide or tetraalkyl ammonium hydroxide. In the etchant, the sugar alcohol has 0.1 to 10 parts by weight for every 100 parts by weight of the basic compound.

公开(公告)号：US20210217861A1

公开(公告)日：2021-07-15

申请号：US17034088

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUN-SEUNG SONG ,  Tae-Yeol Kim ,  Jae-Jik Baek

IPC: H01L29/417 ,  H01L29/40 ,  H01L23/522

Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

公开(公告)号：US09960241B2

公开(公告)日：2018-05-01

申请号：US14989485

申请日：2016-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Kee Sang Kwon ,  Jae-Jik Baek ,  Boun Yoon

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/51 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern protruding from a substrate, gate structures crossing over the active pattern, gate spacers on sidewalls of the gate structures, a source/drain region in the active pattern between the gate structures, and a source/drain contact on and connected to the source/drain region. The source/drain contact includes a first portion between the gate structures and being in contact with the gate spacers, a second portion on the first portion and not being in contact with the gate spacers, and a third portion on the second portion. A first boundary between the second and third portions is at the substantially same height as a top surface of the gate structure.

公开(公告)号：US20140206169A1

公开(公告)日：2014-07-24

申请号：US13834118

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hoon Cha ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Young-Sang Youn ,  Jeong-Nam Han

IPC: H01L29/66

CPC classification number: H01L29/66628 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a semiconductor device can include providing a plasma nitrided exposed top surface including an active region and an isolation region. The exposed top surface including the active region and the isolation region can be subjected to etching to form a deeper recess in the active region that in the isolation region and an unmerged epitaxial stress film can be grown in the deeper recess.

Abstract translation: 形成半导体器件的方法可以包括提供包括有源区和隔离区的等离子体氮化的暴露顶表面。 包括有源区和隔离区的暴露的顶表面可以进行蚀刻，以在有源区中形成更深的凹槽，在隔离区中形成较深的凹槽，并且在较深的凹槽中可以生长未熔合的外延应力膜。

公开(公告)号：US10734380B2

公开(公告)日：2020-08-04

申请号：US16158797

申请日：2018-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

公开(公告)号：US09716162B2

公开(公告)日：2017-07-25

申请号：US14697829

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Jae-Jik Baek ,  Myunggeun Song ,  Boun Yoon ,  Sukhun Choi ,  Jeongnam Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/0228 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, and a gate capping pattern on the gate electrode. The gate capping pattern may have a width larger than that of the gate electrode, and the gate capping pattern may include extended portions extending toward the substrate and at least partially covering both sidewalls of the gate electrode.

公开(公告)号：US20230011401A1

公开(公告)日：2023-01-12

申请号：US17932851

申请日：2022-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Tae-Yeol Kim ,  Jae-Jik Baek

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/40

Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.