公开(公告)号：US20240359286A1

公开(公告)日：2024-10-31

申请号：US18384680

申请日：2023-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon KWON ,  Byoungho Kwon ,  Boun Yoon

IPC: B24B37/04 ,  B24B37/10 ,  B24B37/32

CPC classification number: B24B37/042 ,  B24B37/107 ,  B24B37/32

Abstract: A chemical mechanical polishing apparatus includes a first polishing pad for polishing a substrate, a first polishing head on the first polishing pad to support a substrate, and a second polishing pad spaced apart from the first polishing pad in a horizontal direction. A radius of the second polishing pad is less than a radius of the first polishing pad.

公开(公告)号：US10916554B2

公开(公告)日：2021-02-09

申请号：US16793301

申请日：2020-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Miso Shin ,  Myeongan Kwon ,  Chungki Min ,  Byoungho Kwon ,  Boun Yoon

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.

公开(公告)号：US10714472B2

公开(公告)日：2020-07-14

申请号：US15676317

申请日：2017-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kee Sang Kwon ,  Boun Yoon ,  Sangjine Park ,  Myunggeun Song ,  Ki-Hyung Ko ,  Jiwon Yun

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/49

Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.

公开(公告)号：US20190019742A1

公开(公告)日：2019-01-17

申请号：US15868544

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee LEE ,  Jonghyuk Park ,  Choongseob Shin ,  Hyojin Oh ,  Boun Yoon ,  IIyoung Yoon

IPC: H01L23/48 ,  H01L27/108 ,  H01L21/768 ,  H01L25/065

Abstract: A semiconductor may include a substrate including a cell array region and a TSV region, an insulation layer disposed on the substrate and having a recess region on the TSV region, a capacitor on the insulation layer of the cell array region, a dummy support pattern disposed on the insulation layer of the TSV region and overlapping the recess region, when viewed in plan, and a TSV electrode penetrating the dummy support pattern and the substrate.

公开(公告)号：US09960241B2

公开(公告)日：2018-05-01

申请号：US14989485

申请日：2016-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Kee Sang Kwon ,  Jae-Jik Baek ,  Boun Yoon

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/51 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern protruding from a substrate, gate structures crossing over the active pattern, gate spacers on sidewalls of the gate structures, a source/drain region in the active pattern between the gate structures, and a source/drain contact on and connected to the source/drain region. The source/drain contact includes a first portion between the gate structures and being in contact with the gate spacers, a second portion on the first portion and not being in contact with the gate spacers, and a third portion on the second portion. A first boundary between the second and third portions is at the substantially same height as a top surface of the gate structure.

公开(公告)号：US20140248761A1

公开(公告)日：2014-09-04

申请号：US14083654

申请日：2013-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Byung-Kwon Cho ,  Wonsang Choi

IPC: H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/161 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Abstract translation: 使用双金属硅化物层制造半导体器件。 半导体器件包括具有第一和第二区域的衬底，第一区域中的衬底上的第一金属栅电极，第二区域中的衬底上的第二金属栅电极，两侧的衬底上的第一外延层 的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层， 在第一和第二金属硅化物层上的电介质层，通过层间电介质层并电连接到第一和第二金属硅化物层的接触插塞。

公开(公告)号：US20130244414A1

公开(公告)日：2013-09-19

申请号：US13795839

申请日：2013-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Geun Song ,  Ki-Hyung Ko ,  Hayoung Jeon ,  Boun Yoon ,  Jeongnam Han

IPC: H01L29/40

CPC classification number: H01L29/401 ,  H01L21/823462 ,  H01L29/66545

Abstract: Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.

Abstract translation: 制造具有双栅极电介质层的半导体器件的方法可以包括提供包括第一和第二区域的衬底，在衬底上形成具有第一厚度的第一栅极电介质层，形成包括第一和第二沟槽的层间绝缘层， 在所述第一和第二区域中的栅介质层，在所述层间绝缘层和所述第一沟槽和所述第二沟槽的底部上形成牺牲层，形成暴露所述第一沟槽的底部的第一栅极电介质层的牺牲图案，去除所述第一栅极 在所述第一沟槽的底部形成介电层，在所述第一沟槽的底部形成具有第二厚度的第二栅极介电层，去除所述牺牲图案，以及在所述第一和第二栅极电介质层中的每一个上形成栅电极。

公开(公告)号：US20230415304A1

公开(公告)日：2023-12-28

申请号：US18210107

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon Kwon ,  Boun Yoon

IPC: B24B53/017

CPC classification number: B24B53/017

Abstract: A substrate polishing apparatus includes a polishing pad including a magnetic material, a platen having an upper surface to which the polishing pad is attached, a slurry supply unit installed on the polishing pad, a conditioner installed on the polishing pad to be spaced apart from the slurry supply unit in the one direction and configured to fine-polish a surface of the polishing pad, a polishing head installed on the polishing pad to be spaced apart from the conditioner in the one direction and configured to rotate a polishing target, and a magnetic module installed on the polishing pad to be disposed between the conditioner and the polishing head in the one direction and configured to apply magnetic force to polishing pad debris to remove the polishing pad debris.

公开(公告)号：US20230415303A1

公开(公告)日：2023-12-28

申请号：US18097540

申请日：2023-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon Kwon ,  Boun Yoon

IPC: B24B53/017 ,  B24B37/24

CPC classification number: B24B53/017 ,  B24B37/24

Abstract: A polishing apparatus for a substrate, includes: a polishing pad having at least one region formed of a light-transmitting material; a platen on which the polishing pad is disposed on an upper surface thereof, having a groove portion in a region overlapping the polishing pad, and rotatably installed in one direction; a light source unit accommodated in the groove portion of the platen, and emitting light of a predetermined wavelength band to the one region of the polishing pad; a slurry supply unit supplying a slurry containing photocatalyst particles excited by the light of the predetermined wavelength band to the polishing pad; and a polishing head installed on the polishing pad to be spaced apart from the slurry supply unit in the one direction, and rotating a semiconductor substrate in close contact with the polishing pad.

公开(公告)号：US20230201887A1

公开(公告)日：2023-06-29

申请号：US17947242

申请日：2022-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunjin Kim ,  Kiho Bae ,  Boun Yoon ,  Ilyoung Yoon

IPC: B08B3/12 ,  B08B1/04 ,  B08B3/08

CPC classification number: B08B3/12 ,  B08B1/04 ,  B08B3/08

Abstract: A substrate cleaning device, includes: a substrate cleaning module including first and second roll members adjacent to lower and upper surfaces of a substrate, respectively, first and second driving units configured to move the first and second roll members, a first roll cleaning module including a roll receiving region, a first cleaning solution supply unit supplying a first cleaning solution, and an ultrasonic generating unit applying ultrasonic vibrations; a second roll cleaning module including a housing, a brush pad in the housing, and a second cleaning solution supply unit supplying a second cleaning solution; and a control unit controlling the first driving unit so that the first roll member contacts the substrate lower surface or is accommodated in the roll receiving region, and to control the second driving unit so that the second roll member contacts the substrate upper surface or is seated on the brush pad.