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    MEMORY DEVICE
    3.
    发明申请
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20190287595A1

    公开(公告)日：2019-09-19

    申请号：US16128720

    申请日：2018-09-12

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Hideyuki SUGIYAMA ,  Naoharu SHIMOMURA ,  Kazutaka IKEGAMI

    IPC: G11C11/16 ,  H01L43/02 ,  H01L27/22

    Abstract: A memory device according to an embodiment includes: a plurality of memory cells including a storage element having a first and second terminals; a reference resistor having a third and fourth terminals; a first current source electrically connected to the first terminal of the storage element in the selected memory cell; a second current source electrically connected to the third terminal; and a determination circuit that determines the greater one among a resistance value of a storage element of selected one and a resistance value of the reference resistor, the resistance value of the reference resistor being smaller than a middle value between a mean value of first resistance values obtained from the storage elements in the high-resistance state and a mean value of second resistance values obtained from the storage elements in the low-resistance state, and greater than the mean value of the second resistance values.

    CACHE MEMORY AND PROCESSOR SYSTEM
    4.
    发明申请
    CACHE MEMORY AND PROCESSOR SYSTEM 审中-公开
    高速缓存存储器和处理器系统

    公开(公告)号：US20160371189A1

    公开(公告)日：2016-12-22

    申请号：US15257163

    申请日：2016-09-06

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Hiroki NOGUCHI ,  Tetsufumi TANAMOTO ,  Kazutaka IKEGAMI ,  Shinobu FUJITA

    IPC: G06F12/0868 ,  G11C11/16 ,  G06F11/10

    CPC classification number: G06F12/0868 ,  G06F11/1064 ,  G06F12/0811 ,  G06F12/0895 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/502 ,  G06F2212/608 ,  G11C11/1659 ,  G11C11/1675 ,  G11C2029/0411 ,  G11C2207/2245 ,  Y02D10/13

    Abstract: A cache memory has a data cache to store data per cache line, a tag to store address information of the data to be stored in the data cache, a cache controller to determine whether an address by an access request of a processor meets the address information stored in the tag and to control access to the data cache and the tag, and a write period controller to control a period required for writing data in the data cache based on at least one of an occurrence frequency of read errors to data stored in the data cache and a degree of reduction in performance of the processor due to delay in reading the data stored in the data cache.

    Abstract translation: 高速缓存存储器具有数据高速缓存以存储每条高速缓存线的数据，存储要存储在数据高速缓存中的数据的地址信息的标签，高速缓存控制器，用于确定处理器的访问请求的地址是否满足地址信息 存储在标签中并且控制对数据高速缓存和标签的访问;以及写周期控制器，用于基于存储在数据高速缓冲存储器中的数据的读取错误的发生频率中的至少一个来控​​制在数据高速缓存中写入数据所需的时段 数据高速缓存和由于读取存储在数据高速缓存中的数据的延迟而导致的处理器性能的降低程度。

    PROCESSOR
    5.
    发明申请
    PROCESSOR 审中-公开
    处理器

    公开(公告)号：US20140379975A1

    公开(公告)日：2014-12-25

    申请号：US14208132

    申请日：2014-03-13

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Kazutaka IKEGAMI ,  Shinobu Fujita ,  Keiko Abe ,  Kumiko Nomura ,  Hiroki Noguchi

    IPC: G11C14/00

    CPC classification number: G11C14/0081 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3296 ,  G06F12/0895 ,  G06F2212/225 ,  Y02D10/171 ,  Y02D10/172

    Abstract: According to one embodiment, a processor includes a core controlling processing data, a cache data area storing the processing data as cache data in a nonvolatile manner, a first tag area storing a tag data of the cache data in a volatile manner, a second tag area storing the tag data in a nonvolatile manner, a tag controller controlling the tag data. The tag controller determines whether the processing data is stored in the cache data area by acquiring the tag data from one of the first and second tag areas.

    Abstract translation: 根据一个实施例，处理器包括核心控制处理数据，以非易失性方式存储作为高速缓存数据的处理数据的高速缓存数据区域，以易失性方式存储高速缓存数据的标签数据的第一标签区域，第二标签 以非挥发性方式存储标签数据的区域，控制标签数据的标签控制器。 标签控制器通过从第一标签区域和第二标签区域之一获取标签数据来确定处理数据是否存储在高速缓存数据区域中。

    MAGNETIC MEMORY AND MEMORY SYSTEM
    6.
    发明申请
    MAGNETIC MEMORY AND MEMORY SYSTEM 审中-公开

    公开(公告)号：US20190295621A1

    公开(公告)日：2019-09-26

    申请号：US16118880

    申请日：2018-08-31

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Kazutaka IKEGAMI ,  Tomoaki Inokuchi ,  Satoshi Takaya ,  Shinobu Fujita

    IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02

    Abstract: According to one embodiment, a magnetic memory includes: a memory cell including a first magnetoresistive effect element; a reference circuit including a second magnetoresistive effect element having a first resistance state and a third magnetoresistive effect element having a second resistance state; and a read circuit configured to read data in the memory cell based on a first signal based on an output from the memory cell and a second signal based on an output from the reference circuit. At a time of reading of the data, a first voltage is applied to the first magnetoresistive effect element, and a second voltage higher than the first voltage is applied to the second magnetoresistive effect element and the third magnetoresistive effect element.

    MAGNETIC MEMORY
    8.
    发明申请
    MAGNETIC MEMORY 审中-公开

    公开(公告)号：US20180158499A1

    公开(公告)日：2018-06-07

    申请号：US15698242

    申请日：2017-09-07

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Naoharu SHIMOMURA ,  Tomoaki INOKUCHI ,  Hiroki NOGUCHI ,  Katsuhiko KOUI ,  Yuuzo KAMIGUCHI ,  Kazutaka IKEGAMI ,  Hiroaki YODA

    IPC: G11C11/16 ,  H01L27/22 ,  G11C11/15 ,  H01L43/08

    CPC classification number: G11C11/1657 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08

    Abstract: A magnetic memory includes: a first and second terminals; a conductive layer including first to fourth regions, the first and fourth regions being electrically connected to the first and second terminals respectively; a first magnetoresistive element including: a first and second magnetic layers; a first nonmagnetic layer between the first and second magnetic layers; and a third terminal electrically connected to the first magnetic layer; a second magnetoresistive element including: a third and fourth magnetic layers; a second nonmagnetic layer between the third and fourth magnetic layers; and a fourth terminal electrically connected to the third magnetic layer; and a circuit configured to apply a write current between the first terminal and the second terminal and apply a first and second potentials to the third and fourth terminals respectively to write the first and second magnetoresistive elements, the first and second potentials being different from each other.

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