公开(公告)号：US12211902B2

公开(公告)日：2025-01-28

申请号：US17520882

申请日：2021-11-08

Applicant: DENSO CORPORATION

Inventor： Masato Noborio ,  Takehiro Kato ,  Yusuke Yamashita

IPC: H01L29/10 ,  H01L21/04 ,  H01L21/76 ,  H01L21/761 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: In a semiconductor device, a source region is made of an epitaxial layer so as to reduce variation in thickness of a base region and variation in a threshold value. Outside of a cell part, a side surface of a gate trench is inclined relative to a normal direction to a main surface of a substrate, as compared with a side surface of a gate trench in the cell part that is provided by the epitaxial layer of the source region being in contact with the base region.

公开(公告)号：US12170268B2

公开(公告)日：2024-12-17

申请号：US18614310

申请日：2024-03-22

Applicant: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

Inventor： Stephen Morein

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L25/00 ,  H01L25/065 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

Abstract: Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

公开(公告)号：US12148706B2

公开(公告)日：2024-11-19

申请号：US18302197

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xin-Hua Huang ,  Chung-Yi Yu ,  Kuei-Ming Chen

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L29/778

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

公开(公告)号：US20240362394A1

公开(公告)日：2024-10-31

申请号：US18768895

申请日：2024-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan YANG ,  Ting-Wei CHIANG ,  Cheng-I HUANG ,  Hui-Zhong ZHUANG ,  Chi-Yu LU ,  Stefan RUSU

IPC: G06F30/394 ,  H01L21/76 ,  H01L23/522 ,  H01L23/528 ,  H03K19/094

CPC classification number: G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H01L23/5286 ,  H03K19/094 ,  H01L23/5226 ,  H01L2924/0002

Abstract: An integrated circuit structure includes a first and second power rail on a first level, a first and second set of conductive structures on a second level and a first, second and third conductive structure on a third level. The first set of conductive structures is over the first power rail. The second set of conductive structures is over the second power rail. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and a first conductive structure of the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and a second conductive structure of the second set of conductive structures. The third conductive structure overlaps a third conductive structure of the first set of conductive structures and a third conductive structure of the second set of conductive structures.

公开(公告)号：US12080707B2

公开(公告)日：2024-09-03

申请号：US18353907

申请日：2023-07-18

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Tatsuya Naito

IPC: H01L29/06 ,  H01L21/76 ,  H01L21/765 ,  H01L27/06 ,  H01L27/07 ,  H01L29/08 ,  H01L29/10 ,  H01L29/32 ,  H01L29/36 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861

CPC classification number: H01L27/0635 ,  H01L21/76 ,  H01L21/765 ,  H01L27/0727 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/36 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/739 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/8613 ,  H01L29/8611

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type drift region and a second conductivity type base region above the drift region, trench portions at an upper surface of the semiconductor substrate arrayed parallel to one another, each of them penetrating the base region, and mesa portions between respective trench portions. Among the mesa portions, at least one mesa portion includes a first conductivity type first semiconductor region having a higher concentration than the drift region, a second conductivity type second semiconductor region having a higher concentration than the base region, and a first conductivity type accumulation region between the base and drift regions and has a higher concentration than the drift region. The drift region does not extend above the accumulation region. In a longitudinal direction of the trench portions, the accumulation region extends beyond an end portion of the first semiconductor region.

公开(公告)号：US12073170B2

公开(公告)日：2024-08-27

申请号：US18354423

申请日：2023-07-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Hui-Zhong Zhuang ,  Chi-Yu Lu ,  Stefan Rusu

IPC: G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H03K19/094 ,  H01L23/522

CPC classification number: G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H01L23/5286 ,  H03K19/094 ,  H01L23/5226 ,  H01L2924/0002

Abstract: An integrated circuit structure includes a first, second and third power rail extending in a first direction, a first, second and third set of conductive structures extending in the second direction, and being located at a second level, and a first, second and third conductive structure extending in the second direction, and being located at a third level. The first conductive structure overlaps a first conductive structure of the corresponding first, second and third set of conductive structures. The second conductive structure overlaps a second conductive structure of the corresponding first, second and third set of conductive structures. The third conductive structure overlaps a third conductive structure of the corresponding first, second and third set of conductive structures.

公开(公告)号：US12027617B2

公开(公告)日：2024-07-02

申请号：US17515645

申请日：2021-11-01

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Akimasa Kinoshita

IPC: H01L29/78 ,  H01L21/76 ,  H01L21/761 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7811 ,  H01L21/7602 ,  H01L21/761 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

Abstract: A voltage withstanding structure disposed in an edge termination region is a spatial modulation junction termination extension (JTE) structure formed by a combination of a JTE structure and a field limiting ring (FLR) structure. All FLRs configuring the FLR structure are surrounded by an innermost one of p−−-type regions configuring the JTE structure. An innermost one of the FLRs is disposed overlapping a p+-type extension and the innermost one of the p−−-type regions, at a position overlapping a border between the p+-type extension and the innermost one of the p−−-type regions. The FLRs are formed concurrently with p++-type contact regions in an active region and have an impurity concentration substantially equal to an impurity concentration of the p++-type contact regions. An n+-type channel stopper region is formed concurrently with n+-type source regions in the active region and has an impurity concentration substantially equal to an impurity concentration the n+-type source regions.

公开(公告)号：US11984468B2

公开(公告)日：2024-05-14

申请号：US17793489

申请日：2021-05-28

Applicant: TOWER PARTNERS SEMICONDUCTOR CO., LTD. ,  TOWER SEMICONDUCTOR LTD.

Inventor： Masafumi Tsutsui

IPC: H01L27/148 ,  H01L21/76 ,  H01L21/762 ,  H01L27/146 ,  H04N25/70

CPC classification number: H01L27/14818 ,  H01L21/76 ,  H01L21/762 ,  H01L27/146 ,  H01L27/1463 ,  H04N25/70

Abstract: A solid-state imaging device includes a pixel array where pixels are arranged in a matrix. Each of the pixels includes a photoelectric conversion unit configured to generate a signal charge based on incident light, and an element isolation layer having light-shielding properties and surrounding a periphery of the photoelectric conversion unit. The element isolation layers of adjacent ones of the pixels in a row direction and a column direction are isolated from each other. A charge storage layer and a charge trapping layer are provided in each of regions between the element isolation layers of the adjacent ones of the pixels in the row direction and the column direction. The charge storage layer stores the signal charge. The charge trapping layer reduces incidence of light on the charge storage layer.

公开(公告)号：US11978657B2

公开(公告)日：2024-05-07

申请号：US16642132

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Ebony L. Mays ,  Bruce J. Tufts

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02282 ,  H01L29/0649

Abstract: Disclosed herein are methods for manufacturing IC components using bottom-up fill of openings with a dielectric material. In one aspect, an exemplary method includes, first, depositing a solid dielectric liner on the inner surfaces of the openings using a non-flowable process, and subsequently filling the remaining empty volume of the openings with a fill dielectric using a flowable process. Such a combination method may maximize the individual strengths of the non-flowable and flowable processes due to the synergetic effect achieved by their combined use, while reducing their respective drawbacks. Assemblies and devices manufactured using such methods are disclosed as well.

公开(公告)号：US11972952B2

公开(公告)日：2024-04-30

申请号：US17312594

申请日：2019-12-13

Applicant: Lam Research Corporation

Inventor： Ruopeng Deng ,  Xiaolan Ba ,  Tianhua Yu ,  Yu Pan ,  Juwen Gao

IPC: H01L21/76 ,  H01L21/285 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/28562 ,  H01L21/28568 ,  H01L21/76876 ,  H01L21/76877 ,  H10B41/27 ,  H10B43/27

Abstract: Methods and apparatuses are described that provide tungsten deposition with low roughness. In some embodiments, the methods involve co-flowing nitrogen with hydrogen during an atomic layer deposition process of depositing tungsten that uses hydrogen as a reducing agent. In some embodiments, the methods involve depositing a cap layer, such as tungsten oxide or amorphous tungsten layer, on a sidewall surface of a 3D NAND structure. The disclosed embodiments have a wide variety of applications including depositing tungsten into 3D NAND structures.