公开(公告)号：US20250069645A1

公开(公告)日：2025-02-27

申请号：US18946954

申请日：2024-11-14

Applicant: CXMT CORPORATION

Inventor： Zhiqiang ZHANG

IPC: G11C11/4076 ,  G11C11/408 ,  H03K19/20

Abstract: Provided are a control circuit, a control method, and a memory. The control circuit includes: an input control circuit, configured to generate a first drive control signal and a second drive control signal based on a command/address control signal and a command/address inversion signal; an input processing circuit, configured to generate a first intermediate command/address signal based on the first drive control signal and the second drive control signal when the command/address control signal is in an enabled state, that the circuit is in a power down mode being indicated when the command/address control signal is in the enabled state; and a logic decoding circuit, configured to generate a power down mode exit signal in the power down mode based on the command/address inversion signal and the first intermediate command/address signal.

公开(公告)号：US12237003B2

公开(公告)日：2025-02-25

申请号：US17881180

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Zhenming Zhou

IPC: G11C16/04 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096

Abstract: A memory subsystem receives a first read command and a second read command. Responsive to determining that the first read command originated from a host system, the memory subsystem selects a reverse read trim setting. Responsive to determining that the second read command did not originate from the host system, the memory subsystem selects a forward read trim setting. The memory subsystem executes the first read command using the reverse read trim setting. The memory subsystem executes the second read command using the forward read trim setting.

公开(公告)号：US20250061935A1

公开(公告)日：2025-02-20

申请号：US18796915

申请日：2024-08-07

Applicant: Rambus Inc.

Inventor： Dongyun LEE ,  Mark D. KELLAM ,  Joohee KIM

IPC: G11C11/4076 ,  G11C11/4074 ,  G11C11/419

Abstract: An interposer interconnecting a first integrated circuit and a second integrated circuit includes active circuitry. The “active” interposer converts high-speed signals into lower-speed, but more parallelized, signals for transmission across the active interposer. The parallelized signals may be buffered or amplified at intervals while crossing the active interposer. The high-speed to low-speed, and back, conversions may be performed by an appropriately configured and controlled multiplexer/demultiplexer circuitry The supply voltages for some interposer circuits may be different than the supply voltages for the interfaces with the first and second integrated circuit. One or more of the interconnected integrated circuits may supply, and/or calibrate the supply voltages for the interposer circuitry. Timing signals provided by one or more of the interconnected integrated circuits may also be calibrated using circuitry on the active interposer.

公开(公告)号：US12229435B2

公开(公告)日：2025-02-18

申请号：US18412731

申请日：2024-01-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Torsten Partsch

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/065

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

公开(公告)号：US20250046363A1

公开(公告)日：2025-02-06

申请号：US18923604

申请日：2024-10-22

Applicant: CXMT Corporation

Inventor： Yanpeng XIE ,  Zequn HUANG ,  Dong HU

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/4093

Abstract: Embodiments of the present disclosure provide a signal processing circuit and a memory. A command decoding circuit is included, which includes: a preprocessing circuit, configured to: receive a first chip select signal corresponding to previous one cycle of a current cycle corresponding to a current chip select signal and a first command signal corresponding to the previous one cycle of the current cycle corresponding to signal, and perform a logical operation on the first chip select signal and the first command signal to generate a first chip select identifier signal; and an operation circuit, connected to the preprocessing circuit, and configured to: receive the first chip select identifier signal and the current chip select signal, and generate a decoded command corresponding to the current chip select signal when the current chip select signal is in an enabled state and the first chip select identifier signal is in a disabled state.

公开(公告)号：US20250037752A1

公开(公告)日：2025-01-30

申请号：US18539060

申请日：2023-12-13

Applicant: SK hynix Inc.

Inventor： Joon Hong PARK ,  Jeong Je PARK ,  Sang Sic YOON ,  Jong Hyuck CHOI

IPC: G11C11/4076

Abstract: A semiconductor device includes a frequency division circuit configured to generate a first division clock and a second division clock by dividing a frequency of a clock, and an internal command generation circuit configured to generate an internal command based on a command in synchronization with the first division clock and the second division clock, configured to latch, in a pipe latch, a phase detection signal that is generated based on the timing at which the command is received, and configured to compensate for generation timing of the internal command based on the phase detection signal that has been latched in the pipe latch.

公开(公告)号：US12206420B2

公开(公告)日：2025-01-21

申请号：US18223101

申请日：2023-07-18

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yi-Gyeong Kim ,  Young-Su Kwon ,  Su-Jin Park ,  Young-Deuk Jeon ,  Min-Hyung Cho ,  Jae-Woong Choi

IPC: H03K5/156 ,  G06F1/12 ,  G11C11/4076 ,  H03K5/131 ,  H03K5/135 ,  H03L7/081 ,  H03K5/00

Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.

公开(公告)号：US12197354B2

公开(公告)日：2025-01-14

申请号：US18239689

申请日：2023-08-29

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Frederick A Ware

IPC: G06F13/40 ,  G06F9/48 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4094 ,  H04L47/50

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

公开(公告)号：US20250014629A1

公开(公告)日：2025-01-09

申请号：US18888626

申请日：2024-09-18

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Marco Sforzin ,  Daniele Balluchi

IPC: G11C11/406 ,  G11C11/4076

Abstract: A method including obtaining temperature values of a region of the non-volatile memory, each temperature value obtained at a given time instant, for each obtained temperature value at each given time instant, calculating the value of an operating function representative of an operating condition of the non-volatile memory, the value such operating function being time-dependent according to the temperature time-variation of the region of the non-volatile memory, summing subsequent computed values of the operating function to obtain an accumulated value being representative of an elapsed fraction of a time limit associated with the region of the non-volatile memory, comparing the accumulated value with a threshold value, and, based on the comparison, performing a management operation on the cells of the region of the non-volatile memory when the accumulated value has a magnitude equal or greater than the threshold value.

公开(公告)号：US20250006248A1

公开(公告)日：2025-01-02

申请号：US18749370

申请日：2024-06-20

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Antonino Caprì

IPC: G11C11/408 ,  G11C11/4076

Abstract: Methods, systems, and devices related to row activation indication registers are disclosed. A first register can be coupled to a memory device and configured to store an indication of a first number of bit locations of a row address corresponding to the memory device to use in association with optimization of a row precharge time (tRP) of the memory device. A second register can be coupled to the memory device and configured to store an indication of a second number of bit locations of the row address to use in association with optimization of a row address to column address delay (tRCD) of the memory device.