公开(公告)号：US20230230622A1

公开(公告)日：2023-07-20

申请号：US17839217

申请日：2022-06-13

Applicant: SK hynix Inc.

Inventor： Joon Hong PARK ,  Dae Han KWON

IPC: G11C7/10 ,  G11C7/04 ,  G11C7/22 ,  G11C8/18 ,  G06F7/544

CPC classification number: G11C7/1039 ,  G11C7/1063 ,  G11C7/04 ,  G11C7/22 ,  G11C8/18 ,  G06F7/5443

Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication and accumulation (MAC) units, each of the MAC units including a memory bank and a MAC operator, and a control circuit configured to control the plurality of MAC units to perform an all MAC mode operation in which MAC operations are performed in all MAC units, among the plurality of MAC units, or a dispersion MAC mode operation in which the MAC operations are performed in some MAC units, among the plurality of MAC units.

公开(公告)号：US20210279129A1

公开(公告)日：2021-09-09

申请号：US17137699

申请日：2020-12-30

Applicant: SK hynix Inc.

Inventor： Seong Ju LEE ,  Joon Hong PARK ,  Young Mok JEONG

IPC: G06F11/10

Abstract: A memory device includes a first comparison circuit suitable for comparing read data read from a plurality of memory cells with write data written in the memory cells and outputting a comparison result, a path selection circuit suitable for transferring selected data selected among the read data and test data as read path data based on the comparison result of the first comparison circuit, and an output data alignment circuit suitable for converting the read path data into serial data to output the serial data as output data.

公开(公告)号：US20250037752A1

公开(公告)日：2025-01-30

申请号：US18539060

申请日：2023-12-13

Applicant: SK hynix Inc.

Inventor： Joon Hong PARK ,  Jeong Je PARK ,  Sang Sic YOON ,  Jong Hyuck CHOI

IPC: G11C11/4076

Abstract: A semiconductor device includes a frequency division circuit configured to generate a first division clock and a second division clock by dividing a frequency of a clock, and an internal command generation circuit configured to generate an internal command based on a command in synchronization with the first division clock and the second division clock, configured to latch, in a pipe latch, a phase detection signal that is generated based on the timing at which the command is received, and configured to compensate for generation timing of the internal command based on the phase detection signal that has been latched in the pipe latch.

公开(公告)号：US20240320172A1

公开(公告)日：2024-09-26

申请号：US18351910

申请日：2023-07-13

Applicant: SK hynix Inc.

Inventor： Joon Hong PARK ,  Dae Han KWON

IPC: G06F13/20

CPC classification number: G06F13/20

Abstract: A semiconductor chip includes a first input/output control circuit configured to generate a first input/output switching signal that controls a first data input/output operation on a first data input/output group according to a first input voltage generated based on an operation voltage, and a second input/output control circuit configured to generate a second input/output switching signal that controls a second data input/output operation on a second data input/output group according to a second input voltage generated based on the operation voltage.

公开(公告)号：US20240071443A1

公开(公告)日：2024-02-29

申请号：US18089322

申请日：2022-12-27

Applicant: SK hynix Inc.

Inventor： Joon Hong PARK

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C7/1093

Abstract: A semiconductor device includes a control circuit configured to generate a buffer enable signal that is enabled when patterns of a strobe signal and an inverted strobe signal are preset patterns after the start of a write operation and configured to generate an internal strobe signal by dividing frequencies of an input strobe signal and an inverted input strobe signal, and a buffer circuit configured to generate the input strobe signal and the inverted input strobe signal from the strobe signal and the inverted strobe signal that are received when the buffer enable signal is enabled and configured to generate transfer data by receiving data for performing the write operation when the buffer enable signal is enabled.

公开(公告)号：US20230206967A1

公开(公告)日：2023-06-29

申请号：US17736465

申请日：2022-05-04

Applicant: SK hynix Inc.

Inventor： Joon Hong PARK

IPC: G11C7/10 ,  G06F7/544

CPC classification number: G11C7/106 ,  G11C7/1087 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1048 ,  G06F7/5443

Abstract: An accumulator includes an accumulating adder configured to add input data and latch data to output accumulation data, a selector configured to receive external data and the accumulation data, and output one of the external data and the accumulation data as selection data, and a latch circuit configured to latch the selection data output from the selector to transmit latched selection data into the accumulating adder as the latch data.