公开(公告)号：US20250046363A1

公开(公告)日：2025-02-06

申请号：US18923604

申请日：2024-10-22

Applicant: CXMT Corporation

Inventor： Yanpeng XIE ,  Zequn HUANG ,  Dong HU

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/4093

Abstract: Embodiments of the present disclosure provide a signal processing circuit and a memory. A command decoding circuit is included, which includes: a preprocessing circuit, configured to: receive a first chip select signal corresponding to previous one cycle of a current cycle corresponding to a current chip select signal and a first command signal corresponding to the previous one cycle of the current cycle corresponding to signal, and perform a logical operation on the first chip select signal and the first command signal to generate a first chip select identifier signal; and an operation circuit, connected to the preprocessing circuit, and configured to: receive the first chip select identifier signal and the current chip select signal, and generate a decoded command corresponding to the current chip select signal when the current chip select signal is in an enabled state and the first chip select identifier signal is in a disabled state.

公开(公告)号：US20250046360A1

公开(公告)日：2025-02-06

申请号：US18923615

申请日：2024-10-22

Applicant: CXMT Corporation

Inventor： Yanpeng XIE ,  Zequn HUANG ,  Kai DAI ,  Dong HU

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: The present disclosure provides a clock signal generation circuit and method, and a memory. The circuit includes: a command predecoding circuit, configured to decode partial command bits in a command, to obtain a predecoded command signal; a command decoding circuit, configured to decode the command, to obtain an internal command signal; a counter circuit, configured to count a clock cycle based on an initial clock signal, to generate a first counting signal and a second counting signal; and a clock signal interception circuit, connected to the command predecoding circuit, the command decoding circuit, and the counter circuit, and configured to intercept the initial clock signal based on the predecoded command signal, the internal command signal, the first counting signal, and the second counting signal, to obtain a target clock signal. According to embodiments of the present disclosure, a dynamic loss of the memory can be reduced.