知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

41 records (took 0.045 seconds)

    Techniques for atomic write operations
    1.
    发明授权
    Techniques for atomic write operations 有权

    公开(公告)号：US12112064B2

    公开(公告)日：2024-10-08

    申请号：US17647699

    申请日：2022-01-11

    Applicant: Micron Technology, Inc.

    Inventor： Luca Porzio ,  Christian M. Gyllenskog ,  Dionisio Minopoli

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

    Abstract: Methods, systems, and devices for techniques for atomic write operations are described. A memory system may determine a set of pages for an atomic write operation in which data associated with a write command is linked together for writing to a non-volatile memory. The memory system may write, to the non-volatile memory, metadata that indicates the set of pages is associated with the atomic write operation. Based on the metadata, the memory system may determine whether each page of the set of pages has been written with data for the atomic write operation. The memory system may then communicate to a host system an indication of a completion status for the atomic write operation based on determining whether each page of the set of pages has been written with the data for the atomic write operation.

    Caching or evicting host-resident translation layer based on counter
    2.
    发明授权
    Caching or evicting host-resident translation layer based on counter 有权

    公开(公告)号：US11693781B2

    公开(公告)日：2023-07-04

    申请号：US16947851

    申请日：2020-08-20

    Applicant: Micron Technology, Inc.

    Inventor： Dionisio Minopoli ,  Daniele Balluchi

    IPC: G06F12/0866

    CPC classification number: G06F12/0866 ,  G06F2212/311 ,  G06F2212/7201

    Abstract: A processing device in a memory system receives, from a host system, a read command comprising an indication of a sub-region of a logical address space of a memory device. The processing device increments a counter associated with a region of the logical address space, the region comprising a plurality of sub-regions including the sub-region, the counter to track a number of read operations performed on the plurality of sub-regions of the region, wherein the counter is periodically decremented in response to an occurrence of a recency event on the memory device. The processing device further determines whether a value of the counter satisfies a cacheable threshold criterion and, responsive to the value of the counter satisfying the cacheable threshold criterion, sends, to the host system, a recommendation to activate the sub-region.

    TECHNIQUES FOR ATOMIC WRITE OPERATIONS
    3.
    发明公开
    TECHNIQUES FOR ATOMIC WRITE OPERATIONS 审中-公开

    公开(公告)号：US20230205457A1

    公开(公告)日：2023-06-29

    申请号：US17647699

    申请日：2022-01-11

    Applicant: Micron Technology, Inc.

    Inventor： Luca Porzio ,  Christian M. Gyllenskog ,  Dionisio Minopoli

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

    Abstract: Methods, systems, and devices for techniques for atomic write operations are described. A memory system may determine a set of pages for an atomic write operation in which data associated with a write command is linked together for writing to a non-volatile memory. The memory system may write, to the non-volatile memory, metadata that indicates the set of pages is associated with the atomic write operation. Based on the metadata, the memory system may determine whether each page of the set of pages has been written with data for the atomic write operation. The memory system may then communicate to a host system an indication of a completion status for the atomic write operation based on determining whether each page of the set of pages has been written with the data for the atomic write operation.

    Methods, Devices and Systems for an Improved Management of a Non-Volatile Memory
    4.
    发明申请
    Methods, Devices and Systems for an Improved Management of a Non-Volatile Memory 有权

    公开(公告)号：US20220068367A1

    公开(公告)日：2022-03-03

    申请号：US17404487

    申请日：2021-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Dionisio Minopoli ,  Marco Sforzin ,  Daniele Balluchi

    IPC: G11C11/406 ,  G11C11/4076

    Abstract: A method including obtaining temperature values of at least one region of the non-volatile memory, each temperature value obtained at a given time instant, for each obtained temperature value at each given time instant, calculating the value of an operating function representative of an operating condition of the non-volatile memory, the value such operating function being time-dependent according to the temperature time-variation of such at least one region of the non-volatile memory, summing subsequent computed values of said operating function to obtain an accumulated value being representative of an elapsed fraction of a time limit associated with the at least one region of the non-volatile memory, comparing the accumulated value with a threshold value, and, based on said comparison, performing a management operation on the cells of the at least one region of the non-volatile memory when the accumulated value has a magnitude equal or greater than the threshold value.

    SELF-ADAPTIVE WEAR LEVELING METHOD AND ALGORITHM
    5.
    发明申请
    SELF-ADAPTIVE WEAR LEVELING METHOD AND ALGORITHM 有权

    公开(公告)号：US20210406169A1

    公开(公告)日：2021-12-30

    申请号：US16962726

    申请日：2019-10-09

    Applicant: Micron Technology, Inc.

    Inventor： Dionisio Minopoli ,  Daniele Balluchi ,  Gianfranco Ferrante

    IPC: G06F12/02 ,  G06F12/06

    Abstract: A memory device is provided. The memory device comprises: a plurality of memory cells, each memory cell being programmable to at least two logic states, each logic state corresponding to a respective nominal electric resistance value of the memory cell, the plurality of memory cells comprising a first group of memory cells and a second group of memory cells, the memory cells of the second group being programmed to a predefined logic state of said at least two logic states; a memory controller coupled to the plurality of memory cells and configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation to assess the logic state thereof. The memory controller is further configured to: apply the reading voltage to the memory cells of the second group to assess the logic state thereof; if the logic state of at least one memory cell of the second group is assessed to be different from said predefined logic state, perform a refresh operation of the memory cells of the first group by applying thereto a recovery voltage higher than the reading voltage to assess the logic state thereof and then reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.

    Logical to physical table fragments
    6.
    发明授权
    Logical to physical table fragments 有权

    公开(公告)号：US10592427B2

    公开(公告)日：2020-03-17

    申请号：US16052921

    申请日：2018-08-02

    Applicant: Micron Technology, Inc.

    Inventor： Daniele Balluchi ,  Dionisio Minopoli

    IPC: G06F12/1009

    Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.

    LOGICAL TO PHYSICAL TABLE FRAGMENTS
    7.
    发明申请
    LOGICAL TO PHYSICAL TABLE FRAGMENTS 审中-公开

    公开(公告)号：US20200050554A1

    公开(公告)日：2020-02-13

    申请号：US16655769

    申请日：2019-10-17

    Applicant: Micron Technology, Inc.

    Inventor： Daniele Balluchi ,  Dionisio Minopoli

    IPC: G06F12/1009

    Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.

    Host-resident translation layer write command
    10.
    发明授权
    Host-resident translation layer write command 有权

    公开(公告)号：US11656983B2

    公开(公告)日：2023-05-23

    申请号：US17302966

    申请日：2021-05-17

    Applicant: Micron Technology, Inc.

    Inventor： Daniele Balluchi ,  Dionisio Minopoli

    IPC: G06F12/02 ,  G06F12/1045 ,  G06F12/0868

    CPC classification number: G06F12/0246 ,  G06F12/0868 ,  G06F12/1054 ,  G06F12/1063 ,  G06F2212/7201

    Abstract: A processing device in a memory system receives, from a host system, a host-resident translation layer read command comprising a physical address of data to be read from a memory device, wherein the physical address is indicated in at least a portion of a translation layer entry previously provided to the host system with a response to a host-resident translation layer write command and stored in a host-resident translation layer mapping table. The processing device further performs a read operation to read the data stored at the physical address from the memory device and sends, to the host system, the data from the physical address of the memory device.

Patent Agency Ranking