公开(公告)号：US12206420B2

公开(公告)日：2025-01-21

申请号：US18223101

申请日：2023-07-18

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yi-Gyeong Kim ,  Young-Su Kwon ,  Su-Jin Park ,  Young-Deuk Jeon ,  Min-Hyung Cho ,  Jae-Woong Choi

IPC: H03K5/156 ,  G06F1/12 ,  G11C11/4076 ,  H03K5/131 ,  H03K5/135 ,  H03L7/081 ,  H03K5/00

Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.