公开(公告)号：US5480818A

公开(公告)日：1996-01-02

申请号：US15512

申请日：1993-02-09

Applicant: Tomotaka Matsumoto ,  Jun Inoue ,  Teruhiko Ichimura ,  Yuji Murata ,  Junichi Watanabe ,  Yoshio Nagahiro ,  Mari Hodate ,  Kenichi Oki ,  Masahiro Okabe

Inventor： Tomotaka Matsumoto ,  Jun Inoue ,  Teruhiko Ichimura ,  Yuji Murata ,  Junichi Watanabe ,  Yoshio Nagahiro ,  Mari Hodate ,  Kenichi Oki ,  Masahiro Okabe

IPC: H01L21/205 ,  H01L21/336 ,  H01L21/86 ,  H01L29/78 ,  H01L29/786

CPC classification number: C23C16/45525 ,  C23C16/403 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/86 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/7833 ,  H01L29/78621 ,  H01L29/78675 ,  H01L29/78678 ,  Y10S148/15 ,  Y10S148/169

Abstract: A crystal silicon film deposited on an insulating film made of a binary system material or a binary system semiconductor film formed by an atomic layer deposition method has a grain as large as approximately 200 nm. Thus, the mobility of carriers is increased. The crystal silicon thereof is grown within a temperature range of 250.degree. C. to 400.degree. C. Accordingly, when a planar type thin film transistor, an inverted stagger type thin film transistor or a stagger type thin film transistor is formed using crystal silicon formed on these films made of a binary system material, transistor characteristics thereof are improved. Further, when an impurity containing silicon film is formed by a chemical vapor deposition method between a source electrode and a drain electrode of a thin film transistor and a silicon film connected to these electrodes, and a flow rate of impurity containing gas is regulated so that impurity density becomes larger as approaching to the source electrode and the drain electrode, a leakage current in an OFF-state of the transistor is reduced. Since the impurity containing silicon film is grown by a chemical vapor deposition method in this case, the impurity density thereof can be controlled easily and the control accuracy is also improved.

Abstract translation: 沉积在由二元系材料制成的绝缘膜上的晶体硅膜或通过原子层沉积法形成的二元系统半导体膜具有大至约200nm的晶粒。 因此，载波的移动性增加。 其晶体硅在250℃至400℃的温度范围内生长。因此，当使用形成的晶体硅形成平面型薄膜晶体管，反向交错型薄膜晶体管或交错型薄膜晶体管时 在由二元系材料制成的这些膜上，其晶体管特性得到改善。 此外，当通过化学气相沉积法在薄膜晶体管的源电极和漏电极与连接到这些电极的硅膜之间形成含硅膜的杂质时，调节含杂质气体的流量，使得 随着接近源电极和漏电极的杂质密度变大，晶体管截止状态下的漏电流减小。 由于在这种情况下通过化学气相沉积法生长含有杂质的硅膜，因此可以容易地控制其杂质浓度，并且还提高了控制精度。

公开(公告)号：US5186718A

公开(公告)日：1993-02-16

申请号：US685976

申请日：1991-04-15

Applicant: Avi Tepman ,  Howard Grunes ,  Sasson Somekh ,  Dan Maydan

Inventor： Avi Tepman ,  Howard Grunes ,  Sasson Somekh ,  Dan Maydan

IPC: H01L21/00 ,  H01L21/677

CPC classification number: H01L21/67167 ,  H01L21/67184 ,  H01L21/67742 ,  Y10S148/006 ,  Y10S148/169 ,  Y10T29/41 ,  Y10T29/413

Abstract: A processing system for workpieces such as semiconductor wafers is disclosed which incorporates multiple, isolated vacuum stages between the cassette load lock station and the main vacuum processing chambers. A vacuum gradient is applied between the cassette load lock and the main processing chambers to facilitate the use of a very high degree of vacuum in the processing chambers without lengthy pump down times. Separate robot chambers are associated with the vacuum processing chambers and the load lock(s). In addition, separate transport paths are provided between the two robot chambers to facilitate loading and unloading of workpieces. Pre-treatment and post-treatment chambers may be incorporated in the two transport paths.

Abstract translation: 公开了一种用于诸如半导体晶片的工件的处理系统，其在盒加载锁定站和主真空处理室之间并入多个隔离的真空级。 在盒式加载锁和主处理室之间施加真空梯度，以便在处理室中使用非常高的真空度，而不需要冗长的抽空时间。 分离的机器人腔室与真空处理室和负载锁相关联。 另外，在两个机器人室之间提供单独的输送路径，以便于加工和卸载工件。 预处理和后处理室可以并入两个运输路径中。

公开(公告)号：US5182221A

公开(公告)日：1993-01-26

申请号：US714235

申请日：1991-06-12

Applicant: Junichi Sato

Inventor： Junichi Sato

IPC: H01L21/76 ,  H01L21/31 ,  H01L21/316 ,  H01L21/762

CPC classification number: H01L21/02164 ,  H01L21/022 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/76229 ,  Y10S148/025 ,  Y10S148/026 ,  Y10S148/043 ,  Y10S148/118 ,  Y10S148/169

Abstract: A method of filling a recess so that it is flat with a material by a bias ECR-CVD process is capable of depositing the recess with the material without resulting in the increase in the aspect ratio of the recess with the progress of the deposition process and without forming any voids in the material filling up the recess. A method in accordance with the present invention is characterized in that the bias ECR-CVD process is controlled so as to meet a condition expressed by: R=2y/x, where R is the deposition rate ratio, namely, the ratio of a vertical deposition rate at which the material is deposited on the vertical side surface of the recess to a deposition rate at which the material deposited on the horizontal bottom surface of the recess, x is the width of the recess and y is the depth of the recess. In another method of filling a recess flat with a material by a bias ECR-CVD process in accordance with the present invention alternately a deposition cycle using a source gas containing a silicon-containing gas and a deposition cycle using a source gas containing a silicon hydride to obviate the adverse influence of a layer of the material formed by the deposition process using the source gas containing a silicon-containing organic gas and containing carbon on the performance of the device are used.

Abstract translation: 通过偏压ECR-CVD工艺填充凹陷以使其与材料平坦的方法能够与材料沉积凹槽，而不会随着沉积过程的进行而增加凹部的纵横比， 而不会在填充凹槽的材料中形成任何空隙。 根据本发明的方法的特征在于，控制偏压ECR-CVD工艺以满足以下表达的条件：R = 2y / x，其中R是沉积速率比，即垂直 将材料沉积在凹槽的垂直侧表面上的沉积速率到沉积在凹槽的水平底表面上的材料的沉积速率，x是凹部的宽度，y是凹部的深度。 在根据本发明的通过偏压ECR-CVD工艺填充具有材料的凹部的另一种方法中，交替地使用包含含硅气体的源气体和使用含有氢化硅的源气体的沉积循环的沉积循环 为了消除使用包含含硅有机气体并含有碳的源气体的沉积工艺形成的材料层对器件的性能的不利影响。

公开(公告)号：US5120393A

公开(公告)日：1992-06-09

申请号：US639788

申请日：1991-01-10

Applicant: Minoru Kubo ,  Tadashi Narusawa

Inventor： Minoru Kubo ,  Tadashi Narusawa

IPC: C30B23/08 ,  C30B23/02 ,  H01L21/203

CPC classification number: C30B23/02 ,  Y10S148/006 ,  Y10S148/046 ,  Y10S148/048 ,  Y10S148/169

Abstract: Flatness of atomic-accuracy is achieved in an MBE epitaxial growth process by imparting kinetic energy to atoms absorbed on a substrate by means of irradiation by ion-beam for surface bombardment. Ion-beam surface bombardment may also be used for evaluation. The molecular-beam for epitaxial growth and the ion bombardment for surface energization and surface evaluation may all be operated in a pulse mode and synchronized so that evaluation and growth are conducted alternately while growth and energization are conducted simultaneously.

Abstract translation: 在MBE外延生长过程中，通过用离子束照射表面轰击的吸收在基底上的原子赋予原子精度的平坦度。 离子束表面轰击也可用于评估。 用于外延生长的分子束和用于表面激励和表面评估的离子轰击都可以以脉冲模式操作并且同步，使得评估和生长在同时进行生长和通电的同时进行。

公开(公告)号：US5062771A

公开(公告)日：1991-11-05

申请号：US325910

申请日：1989-03-20

Applicant: Akihiko Satou ,  Tadao Kusaka ,  Shigeo Tomiyama ,  Kouzi Aoki ,  Ichiro Gyobu ,  Kimio Muramatsu ,  Hiroaki Sakamoto ,  Shinjiroo Ueda ,  Masahiro Mase ,  Takashi Nagaoka

Inventor： Akihiko Satou ,  Tadao Kusaka ,  Shigeo Tomiyama ,  Kouzi Aoki ,  Ichiro Gyobu ,  Kimio Muramatsu ,  Hiroaki Sakamoto ,  Shinjiroo Ueda ,  Masahiro Mase ,  Takashi Nagaoka

IPC: B01J3/00 ,  C23C16/44 ,  F04D19/04

CPC classification number: B01J3/006 ,  C23C16/4412 ,  F04D17/168 ,  F04D19/046 ,  F04D23/008 ,  Y10S148/022 ,  Y10S148/03 ,  Y10S148/169 ,  Y10S438/909

Abstract: This invention concerns a production method and a processing apparatus for semiconductor devices, as well as an evacuating apparatus used for the processing apparatus. According to this invention, since the evacuation system of pressure-reduction processing apparatus for conducting various wafer processings during production steps of semiconductor devices is constituted only with oil-free vacuum pump, deleterious oil contaminations or carbonation products of oils produced from oils upon heating are not present in the pressure-reducing processing chamber as compared with conventional pressure-reducing processing apparatus using a vacuum oil pump as an evacuation pump and the production method of semiconductor devices using such apparatus. Accordingly, highly clean evacuated condition can be attained and, in addition, semiconductor devices at high reliability and with no degradation in the electric characteristics can be obtained by using the pressure-reducing processing apparatus having such a highly clean processing chamber.

公开(公告)号：US5013683A

公开(公告)日：1991-05-07

申请号：US300266

申请日：1989-01-23

Applicant: Pierre M. Petroff ,  Herbert Kroemer

Inventor： Pierre M. Petroff ,  Herbert Kroemer

IPC: H01L21/20 ,  H01L21/203 ,  H01L21/337 ,  H01L29/15

CPC classification number: B82Y10/00 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02658 ,  H01L29/151 ,  H01L29/158 ,  H01L29/66924 ,  Y10S117/902 ,  Y10S148/025 ,  Y10S148/097 ,  Y10S148/16 ,  Y10S148/169 ,  Y10S438/962

Abstract: A method for growing a superlattice structure on a substrate. First, a periodic array of monoatomic surface steps are created on the surface of the substrate at an area to have the superlattice structure grown thereon. There is apparatus for creating a beam of a material being input thereto and for selectively including or not including respective ones of a plurality of materials within the beam. The beam is directed at the steps of the substrate. Finally, logic causes control apparatus to include and not include respective ones of the materials within the beam in a pre-established pattern of time periods which will cause the materials to be deposited on the steps in a series of stacked monolayers. Tilted Superlattices (TSLs) and Coherent Tilted Superlattices (CTSLs) are created. The method can create pseudo ternary semiconductor alloys as part of a CTSL by employing at least two binary compound semiconductor alloys in the deposition process. It can also create a quantum wire superlattice by sandwiching a thin CTSL layer between two wider band gap layers. Additionally, it can create a tilted superlattice with zero misfit strain by using three binary compounds to produce a pseudo-ternary compound in a direction parallel to the substrate normal while the tilted superlattice structure provides a desired band gap in a direction parallel to the substrate surface. One may form the CTSL as part of a field effect transistor (FET) wherein the CTSL is part of the FET gate or form the CTSL as the cladding layers of a quantum wire laser having a GaAs active layer.

Abstract translation: 一种在衬底上生长超晶格结构的方法。 首先，在衬底的表面上在其上生长超晶格结构的区域上产生单原子表面台阶的周期性阵列。 存在用于产生输入到其中的材料束的设备，并且用于选择性地包括或不包括在梁内的多个材料中的相应材料。 光束指向基板的台阶。 最后，逻辑使得控制装置包括并且不包括预先建立的时间段模式中的束内的材料中的相应材料，这将使材料沉积在一系列堆叠单层中的台阶上。 创建了倾斜超晶格（TSL）和相干倾斜超晶格（CTSL）。 该方法可以通过在沉积工艺中采用至少两种二元化合物半导体合金来制造伪三元半导体合金作为CTSL的一部分。 它还可以通过在两个较宽的带隙层之间夹入薄的CTSL层来产生量子线超晶格。 另外，它可以通过使用三种二元化合物在平行于衬底法线的方向上产生伪三元化合物而产生具有零失配应变的倾斜超晶格，同时倾斜超晶格结构在平行于衬底表面的方向上提供期望的带隙 。 可以将CTSL形成为场效应晶体管（FET）的一部分，其中CTSL是FET栅极的一部分或形成CTSL作为具有GaAs活性层的量子线激光器的包层。

公开(公告)号：US4910167A

公开(公告)日：1990-03-20

申请号：US120023

申请日：1987-11-13

Applicant: Jhang W. Lee ,  Richard E. McCullough ,  Jack P. Salerno

Inventor： Jhang W. Lee ,  Richard E. McCullough ,  Jack P. Salerno

IPC: H01L21/20 ,  H01L21/205

CPC classification number: H01L21/02546 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02513 ,  H01L21/02543 ,  H01L21/0262 ,  Y10S148/065 ,  Y10S148/072 ,  Y10S148/11 ,  Y10S148/149 ,  Y10S148/169 ,  Y10S438/933

Abstract: A GaAs containing nucleation layer is deposited upon Si, Ge/Si, or other single crystal substrate from triethyl gallium (TEG). Deposition from TEG allows a lower deposition temperature which provides a low level of substrate contamination and improved surface morphology.

Abstract translation: 含Si的成核层由三乙基镓（TEG）沉积在Si，Ge / Si或其它单晶衬底上。 来自TEG的沉积允许较低的沉积温度，其提供低水平的底物污染和改善的表面形态。

公开(公告)号：US4885258A

公开(公告)日：1989-12-05

申请号：US267701

申请日：1988-11-01

Applicant: Shunichi Ishihara ,  Hirokazu Ootoshi ,  Masaaki Hirooka ,  Junichi Hanna ,  Isamu Shimizu

Inventor： Shunichi Ishihara ,  Hirokazu Ootoshi ,  Masaaki Hirooka ,  Junichi Hanna ,  Isamu Shimizu

IPC: H01L27/12 ,  H01L21/205 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/02381 ,  H01L21/02422 ,  H01L21/02425 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  Y10S148/057 ,  Y10S148/169 ,  Y10S438/909

Abstract: There is provided an improved thin-film transistor of which a principal semiconducting layer comprises a layer composed of an amorphous material prepared by (a) introducing (i) a gaseous substance containing atoms capable of becoming constituents for said layer into a film forming chamber having a substrate for thin-film transistor through a transporting conduit for the gaseous substance and (ii) a gaseous halogen series substance having a property to oxidize the gaseous substance into the film forming chamber through a transporting conduit for the gaseous halogen series oxidizing agent, (b) chemically reacting the gaseous substance and the gaseous halogen series agent in the film forming chamber in the absence of a plasma to generate plural kinds of precursors containing exited precursors and (c) forming said layer on the substrate with utilizing at least one kind of those precursors as a supplier.

Abstract translation: 提供了一种改进的薄膜晶体管，其主要半导体层包括由非晶材料构成的层，其通过以下步骤制备：（a）将含有能够成为所述层的成分的原子的气态物质引入到具有 通过用于气态物质的输送导管的薄膜晶体管的基板和（ii）具有通过气态卤素系列氧化剂的输送管道将气态物质氧化成成膜室的性质的气态卤素系列物质（ b）在不存在等离子体的情况下使成膜室中的气态物质和气态卤素系列试剂化学反应，生成多种含有前体前体的前体，和（c）使用至少一种 这些前体作为供应商。

公开(公告)号：US4771013A

公开(公告)日：1988-09-13

申请号：US892681

申请日：1986-08-01

Applicant: Patrick A. Curran

Inventor： Patrick A. Curran

IPC: H01L21/203 ,  H01L21/26 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8226 ,  H01L27/00 ,  H01L27/02 ,  H01L27/06 ,  H01L27/082 ,  H01L29/161 ,  H01L29/73 ,  H01L29/737 ,  H01L27/04 ,  H01L21/20

CPC classification number: H01L29/66242 ,  H01L21/8221 ,  H01L27/0237 ,  H01L27/0605 ,  Y10S148/011 ,  Y10S148/012 ,  Y10S148/142 ,  Y10S148/147 ,  Y10S148/16 ,  Y10S148/164 ,  Y10S148/169

Abstract: A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, and structure formed thereby includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of crystal orientation, which is etched and with three dimensional transistors formed in it. Passivation for and contacts to said circuits are established, and the circuits are interconnected. The high voltage and high power transistors include transistors of an H-bridge circuit, including at least one set of cascode double heterojunction transistors, the analog transistors include a bipolar transistor, and the digital transistors include transistors of a I.sup.2 L circuit. One method for constructing the wafer is by sequentially epitaxially depositing each strata in an UHV silicon-based MBE apparatus. Another method is by constructing guest and host wafers, each containing respective portions of the strata, and fusing said guest and host wafers together.

Abstract translation: 用于集成高电压，高功率，模拟和数字电路以及由此形成的结构的三维双极晶片工艺包括在<100>晶体取向的重施体掺杂单晶硅衬底上的非补偿外延层的晶片，其中 被蚀刻并且其中形成有三维晶体管。 建立对所述电路的钝化和接触，并且电路互连。 高压和高功率晶体管包括H桥电路的晶体管，其包括至少一组共源共栅双异质结晶体管，模拟晶体管包括双极晶体管，并且数字晶体管包括I2L电路的晶体管。 用于构造晶片的一种方法是通过在UHV硅基MBE装置中顺序地外延地沉积每个层。 另一种方法是通过构造客体和主体晶片，每个晶片包含层的相应部分，并将所述客体和主晶片熔合在一起。

公开(公告)号：US4769341A

公开(公告)日：1988-09-06

申请号：US947051

申请日：1986-12-29

Applicant: Sergey Luryi

Inventor： Sergey Luryi

IPC: H01L21/203 ,  H01L21/20 ,  H01L21/205 ,  H01L21/26

CPC classification number: H01L21/0262 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02535 ,  Y10S148/072 ,  Y10S148/097 ,  Y10S148/16 ,  Y10S148/169 ,  Y10S438/933 ,  Y10S438/936

Abstract: A semiconductor device comprising an epitaxially grown tin and Group IV compound semiconductor region on which at least one other semiconductor is grown lattice matched to the adjacent portion of the tin containing region. A large number of semiconductors may thus be grown.