Invention Grant
US4771013A Process of making a double heterojunction 3-D I.sup.2 L bipolar
transistor with a Si/Ge superlattice
失效
制造具有Si / Ge超晶格的双异质结3-D I2L双极晶体管的工艺
- Patent Title: Process of making a double heterojunction 3-D I.sup.2 L bipolar transistor with a Si/Ge superlattice
- Patent Title (中): 制造具有Si / Ge超晶格的双异质结3-D I2L双极晶体管的工艺
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Application No.: US892681Application Date: 1986-08-01
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Publication No.: US4771013APublication Date: 1988-09-13
- Inventor: Patrick A. Curran
- Applicant: Patrick A. Curran
- Applicant Address: TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: TX Dallas
- Main IPC: H01L21/203
- IPC: H01L21/203 ; H01L21/26 ; H01L21/331 ; H01L21/822 ; H01L21/8222 ; H01L21/8226 ; H01L27/00 ; H01L27/02 ; H01L27/06 ; H01L27/082 ; H01L29/161 ; H01L29/73 ; H01L29/737 ; H01L27/04 ; H01L21/20
Abstract:
A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, and structure formed thereby includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of crystal orientation, which is etched and with three dimensional transistors formed in it. Passivation for and contacts to said circuits are established, and the circuits are interconnected. The high voltage and high power transistors include transistors of an H-bridge circuit, including at least one set of cascode double heterojunction transistors, the analog transistors include a bipolar transistor, and the digital transistors include transistors of a I.sup.2 L circuit. One method for constructing the wafer is by sequentially epitaxially depositing each strata in an UHV silicon-based MBE apparatus. Another method is by constructing guest and host wafers, each containing respective portions of the strata, and fusing said guest and host wafers together.
Public/Granted literature
- US5785854A Current and aeration system for wastewater plant Public/Granted day:1998-07-28
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