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    Semiconductor embedded layer technology utilizing selective epitaxial growth methods
    1.
    发明授权
    Semiconductor embedded layer technology utilizing selective epitaxial growth methods 失效
    采用选择性外延生长方法的半导体嵌入层技术

    公开(公告)号：US5032538A

    公开(公告)日：1991-07-16

    申请号：US073912

    申请日：1987-07-07

    申请人： Carl O. Bozler ,  Gary D. Alley ,  William T. Lindley ,  R. Allen Murphy

    发明人： Carl O. Bozler ,  Gary D. Alley ,  William T. Lindley ,  R. Allen Murphy

    IPC分类号： H01L21/20 ,  H01L21/335 ,  H01L21/74 ,  H01L23/482 ,  H01L23/52 ,  H01L23/535 ,  H01L29/772 ,  H01L29/92

    CPC分类号： H01L29/66424 ,  H01L21/743 ,  H01L23/4824 ,  H01L23/52 ,  H01L23/535 ,  H01L28/40 ,  H01L29/7722 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S148/026 ,  Y10S148/053 ,  Y10S148/115 ,  Y10S148/142 ,  Y10S148/164

    摘要： A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is disclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range. With increasing forward base bias the potential in the openings, which is lower than along the metal of the base layer (34), is lowered sufficiently to permit substantial increase in the barrier limited current flow from the collector (38) to emitter (40).A method of fabricating this transistor as well as methods for forming integrated circuit structures are also disclosed. Metal and other layers may be selectively embedded in semiconductor crystal. Embedded metal layers may serve as interconnections between devices. Devices may be in a stacked configuration.

    摘要翻译： 公开了一种可渗透的基极晶体管（30），其包括嵌入半导体晶体（32）中以分离集电极（38）和发射极（40）区域并形成肖特基势垒的金属基底层（34）。 金属基层具有至少一个开口（37），晶体半导体（32）通过该开口连接集电极（38）和发射极（40）区域。 欧姆接触（42,44）制成发射极（38）和集电极（40）区域。 基底层（34）中的所有开口（37）的宽度为与开口中的载流子浓度相对应的零偏置耗尽宽度的量级。 金属层（34）的厚度为该零偏置耗尽宽度的10％量级。 结果，每个开口中的势垒限制了偏压范围下部的电流。 随着正向基极偏压的增加，开口中比基底层（34）的金属低的电位被充分降低，从而可以显着增加从集电器（38）到发射极（40）的阻挡限制电流， 。 还公开了一种制造该晶体管的方法以及用于形成集成电路结构的方法。 金属等层可以选择性地嵌入在半导体晶体中。 嵌入式金属层可用作器件之间的互连。 设备可能处于堆叠配置。

    Self-aligned fabrication process for GaAs MESFET devices
    2.
    发明授权
    Self-aligned fabrication process for GaAs MESFET devices 失效
    GaAs MESFET器件的自对准制造工艺

    公开(公告)号：US4735913A

    公开(公告)日：1988-04-05

    申请号：US860139

    申请日：1986-05-06

    申请人： John R. Hayes

    发明人： John R. Hayes

    IPC分类号： H01L21/285 ,  H01L21/324 ,  H01L21/338 ,  H01L21/265 ,  H01L21/44

    CPC分类号： H01L29/66878 ,  H01L21/28587 ,  H01L21/3245 ,  Y10S148/105 ,  Y10S148/14 ,  Y10S148/142

    摘要： A self-aligned process for fabricating a GaAs semiconductor MESFET by depositing a layer of tungsten over the GaAs substrate, and ion implanting the substrate to provide channel doping. A gate composed of a conductive refractory material is deposited and delineated on the tungsten layer, and source and drain regions are formed in the substrate using the gate as a mask. The resulting device is annealed and contacts are formed to the source and drain regions, and to the gate.

    摘要翻译： 用于通过在GaAs衬底上沉积钨层来制造GaAs半导体MESFET的自对准工艺，以及离子注入衬底以提供沟道掺杂。 在钨层上沉积并描绘由导电耐火材料构成的栅极，并且使用栅极作为掩模在基板中形成源区和漏极区。 所得到的器件被退火，并且与源极和漏极区域以及栅极形成接触。

    Improved surface barrier transistor
    4.
    发明授权
    Improved surface barrier transistor 失效
    改进的表面障碍晶体管

    公开(公告)号：US3614560A

    公开(公告)日：1971-10-19

    申请号：US3614560D

    申请日：1969-12-30

    申请人： IBM

    发明人： ANANTHA NARASIPUR G

    IPC分类号： H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/08 ,  H01L19/00

    CPC分类号： H01L29/0821 ,  H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  Y10S148/142

    摘要： A semiconductor device comprising in combination: a first zone of semiconductive material containing impurity atoms of the acceptor type; a contiguous second zone of semiconductive material containing a predetermined low concentration of impurity atoms of the donor type; a metal layer having an interface with said second zone; and a third zone of relatively highly conductive semiconductive material in contact with said metal layer and containing a high concentration of impurity atoms of either the donor or acceptor type. In a typical device in accordance with this invention the ''''first zone'''' is formed as a P+ diffusion area in the ''''second zone'''' which is of the Nconductivity type of silicon, the ''''metal'''' is platinum, the ''''third zone'''' is formed by P+ diffusion into a monocrystalline silicon wafer, and emitter, base and collector leads are in contact with said first, second and third zones, respectively.

    Method of fabricating a MESFET transistor with gate spaced above source electrode by layer of air or the like
    9.
    发明授权
    Method of fabricating a MESFET transistor with gate spaced above source electrode by layer of air or the like 失效
    制造MESFET晶体管的方法，其栅极通过空气等层间隔开源极电极

    公开(公告)号：US4871687A

    公开(公告)日：1989-10-03

    申请号：US261142

    申请日：1988-10-24

    申请人： Giampiero Donzelli

    发明人： Giampiero Donzelli

    IPC分类号： H01L29/80 ,  H01L21/027 ,  H01L21/285 ,  H01L21/338 ,  H01L21/38 ,  H01L23/48 ,  H01L23/482 ,  H01L29/41 ,  H01L29/423 ,  H01L29/47 ,  H01L29/812

    CPC分类号： H01L29/66863 ,  H01L21/0271 ,  H01L21/28587 ,  H01L23/4821 ,  H01L23/4824 ,  H01L29/42316 ,  H01L29/475 ,  H01L2924/0002 ,  Y10S148/142

    摘要： In a Schottky field effect MESFET transistor including a semiconductor substrate and source, gate and drain electrodes, the electrical resistance of the gate is reduced to substantially zero by implementing the gate electrode as a sheet of metallization which bypasses a portion of the source electrode and which is spaced from the source electrode by a layer of air or the like. The MESFET transistor may be fabricated by providing drain and source electrodes on a semiconductor substrate with the electrodes situated side-by-side. Photoresist is applied over at least the source electrode while leaving exposed (a) a first portion of the substrate surface between the source and drain electrodes and (b) a second portion of the substrate surface situated on an opposite side of the source electrode and which is used as a bonding pad location. Gate metallization is then formed over the photoresist and in contact with the first and second areas of the substrate surface. The metallization may also extend over the drain electrode that is later removed. Upon removal of the photoresist from between the gate and source electrodes, a layer of air of the like dielectrically separates these electrodes from each other. A portion of the gate metallization that overlies the drain electrode may exist as a tail that may have various lengths to make possible a non-critical patterning step for the gate metallization.