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    Active matrix liquid crystal display with variable compensation capacitor
    2.
    发明授权
    Active matrix liquid crystal display with variable compensation capacitor 失效
    有源矩阵液晶显示器带可变补偿电容器

    公开(公告)号：US5369512A

    公开(公告)日：1994-11-29

    申请号：US916361

    申请日：1992-07-21

    Applicant: Kenichi Yanai ,  Tsutomu Tanaka ,  Tatsuya Kakehi ,  Koji Ohgata ,  Kenichi Oki

    Inventor： Kenichi Yanai ,  Tsutomu Tanaka ,  Tatsuya Kakehi ,  Koji Ohgata ,  Kenichi Oki

    IPC: G02F1/1362 ,  G09G3/36 ,  G02F1/1343

    CPC classification number: G02F1/136213 ,  G09G3/3648 ,  G09G3/3659 ,  G02F2201/122 ,  G09G2300/043 ,  G09G2320/0204 ,  G09G2320/0209 ,  G09G2320/0219

    Abstract: An active matrix liquid crystal display apparatus comprises first and second substrates facing each other through a liquid crystal layer. The first substrate has a plurality of scan bus lines, thin film transistors, display electrodes, and reference potential supplying bus lines, and the second substrate has a plurality of stripe-like data bus lines that face the display electrodes. The display electrode has a compensation capacitor for compensating a potential fluctuation occurring in the display electrode after a gate electrode of the thin film transistor is selected. The capacitance of the compensation capacitor is larger during a compensation period than during a storage period in which the gate electrode of the corresponding thin film transistor is not selected.

    Abstract translation: 有源矩阵液晶显示装置包括通过液晶层彼此面对的第一和第二基板。 第一基板具有多条扫描总线，薄膜晶体管，显示电极和参考电位供给总线，第二基板具有面向显示电极的多条条状数据总线。 在选择薄膜晶体管的栅电极之后，显示电极具有用于补偿在显示电极中发生的电位波动的补偿电容器。 补偿电容器的电容在补偿期间比在不选择相应的薄膜晶体管的栅电极的存储期间更大。

    El display device
    4.
    发明授权
    El display device 失效
    El显示设备

    公开(公告)号：US4523189A

    公开(公告)日：1985-06-11

    申请号：US380698

    申请日：1982-05-21

    Applicant: Kazuhiro Takahara ,  Keizo Kurahashi ,  Hiroyuki Gondo ,  Kenichi Oki ,  Shoshin Miura

    Inventor： Kazuhiro Takahara ,  Keizo Kurahashi ,  Hiroyuki Gondo ,  Kenichi Oki ,  Shoshin Miura

    IPC: G09F13/22 ,  G09G3/30

    CPC classification number: G09F13/22 ,  G09G3/30 ,  G09F2013/222 ,  G09G2300/0809 ,  G09G2300/0842

    Abstract: A thin-film EL display device incorporates a MOS active matrix. Each of the MOS transistor arrays is additionally provided in parallel with a Zener diode for the purpose of protecting the device from a high voltage. This Zener diode has a breakdown voltage characteristic corresponding to a difference between a luminous voltage and a non-luminous voltage of an EL display element and clamps the voltage across the MOS transistor, in the "OFF" state, to a voltage less than or equal to non-recoverable breakdown voltage.

    Abstract translation: 薄膜EL显示装置包含MOS有源矩阵。 为了保护器件免受高电压的影响，每个MOS晶体管阵列还与齐纳二极管并联地提供。 该齐纳二极管具有对应于EL显示元件的发光电压和非发光电压之间的差的击穿电压特性，并且将处于“OFF”状态的MOS晶体管两端的电压钳位到小于或等于 到不可恢复的击穿电压。

    Method for forming a film and method for manufacturing a thin film transistor
    6.
    发明授权
    Method for forming a film and method for manufacturing a thin film transistor 失效
    薄膜晶体管的制造方法和薄膜晶体管的制造方法

    公开(公告)号：US5480818A

    公开(公告)日：1996-01-02

    申请号：US15512

    申请日：1993-02-09

    Applicant: Tomotaka Matsumoto ,  Jun Inoue ,  Teruhiko Ichimura ,  Yuji Murata ,  Junichi Watanabe ,  Yoshio Nagahiro ,  Mari Hodate ,  Kenichi Oki ,  Masahiro Okabe

    Inventor： Tomotaka Matsumoto ,  Jun Inoue ,  Teruhiko Ichimura ,  Yuji Murata ,  Junichi Watanabe ,  Yoshio Nagahiro ,  Mari Hodate ,  Kenichi Oki ,  Masahiro Okabe

    IPC: H01L21/205 ,  H01L21/336 ,  H01L21/86 ,  H01L29/78 ,  H01L29/786

    CPC classification number: C23C16/45525 ,  C23C16/403 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/86 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/7833 ,  H01L29/78621 ,  H01L29/78675 ,  H01L29/78678 ,  Y10S148/15 ,  Y10S148/169

    Abstract: A crystal silicon film deposited on an insulating film made of a binary system material or a binary system semiconductor film formed by an atomic layer deposition method has a grain as large as approximately 200 nm. Thus, the mobility of carriers is increased. The crystal silicon thereof is grown within a temperature range of 250.degree. C. to 400.degree. C. Accordingly, when a planar type thin film transistor, an inverted stagger type thin film transistor or a stagger type thin film transistor is formed using crystal silicon formed on these films made of a binary system material, transistor characteristics thereof are improved. Further, when an impurity containing silicon film is formed by a chemical vapor deposition method between a source electrode and a drain electrode of a thin film transistor and a silicon film connected to these electrodes, and a flow rate of impurity containing gas is regulated so that impurity density becomes larger as approaching to the source electrode and the drain electrode, a leakage current in an OFF-state of the transistor is reduced. Since the impurity containing silicon film is grown by a chemical vapor deposition method in this case, the impurity density thereof can be controlled easily and the control accuracy is also improved.

    Abstract translation: 沉积在由二元系材料制成的绝缘膜上的晶体硅膜或通过原子层沉积法形成的二元系统半导体膜具有大至约200nm的晶粒。 因此，载波的移动性增加。 其晶体硅在250℃至400℃的温度范围内生长。因此，当使用形成的晶体硅形成平面型薄膜晶体管，反向交错型薄膜晶体管或交错型薄膜晶体管时 在由二元系材料制成的这些膜上，其晶体管特性得到改善。 此外，当通过化学气相沉积法在薄膜晶体管的源电极和漏电极与连接到这些电极的硅膜之间形成含硅膜的杂质时，调节含杂质气体的流量，使得 随着接近源电极和漏电极的杂质密度变大，晶体管截止状态下的漏电流减小。 由于在这种情况下通过化学气相沉积法生长含有杂质的硅膜，因此可以容易地控制其杂质浓度，并且还提高了控制精度。

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