公开(公告)号：US11798620B2

公开(公告)日：2023-10-24

申请号：US17816612

申请日：2022-08-01

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Russell L. Meyer ,  Agostino Pirovano ,  Andrea Redaelli ,  Lorenzo Fratin ,  Fabio Pellizzer

IPC: G11C11/34 ,  G11C11/56 ,  G11C13/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/005 ,  G11C2013/0052 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/71 ,  G11C2213/76

Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

公开(公告)号：US20190096482A1

公开(公告)日：2019-03-28

申请号：US16140441

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Raymond W. ZENG ,  Mase J. TAUB ,  Kiran PANGAL ,  Sandeep K. GULIANI

IPC: G11C13/00 ,  G11C16/34 ,  G11C16/08 ,  G11C8/06

CPC classification number: G11C13/0028 ,  G11C8/06 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/3418 ,  G11C2013/0052 ,  G11C2013/0092

Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.

公开(公告)号：US20180330781A1

公开(公告)日：2018-11-15

申请号：US16045384

申请日：2018-07-25

Applicant: Micron Technology, Inc.

Inventor： SANDEEP GULIANI ,  Balaji Srinivasan

IPC: G11C13/00 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C13/0004 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/10 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0052 ,  G11C2013/0054 ,  G11C2213/77

Abstract: Apparatuses and methods for accessing a memory cell are described. An example apparatus includes a first voltage circuit coupled to a node and is configured to provide a first voltage to the node and includes a second voltage circuit coupled to a node and is configured to provide a second voltage to the node. A memory cell is coupled to first and second access lines. A decoder circuit is coupled to the node and the first access line, and is configured to selectively couple the first access line to the node. The first voltage circuit is configured to provide the first voltage to the node before the second voltage circuit provides the second voltage to the node, and the second voltage circuit stops providing the second voltage before the node reaches the second voltage.

公开(公告)号：US09858999B2

公开(公告)日：2018-01-02

申请号：US14970911

申请日：2015-12-16

Applicant: Micron Technology, Inc.

Inventor： Alessandro Calderoni ,  Massimo Ferro ,  Paolo Fantini

IPC: G11C11/00 ,  G11C11/14 ,  G11C13/00 ,  G11C29/50 ,  G11C29/00 ,  G11C11/56

CPC classification number: G11C13/004 ,  G11C11/00 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/0069 ,  G11C13/0097 ,  G11C29/006 ,  G11C29/50008 ,  G11C2013/0052 ,  G11C2013/0057

Abstract: The present disclosure includes apparatuses and methods including drift acceleration in resistance variable memory. A number of embodiments include applying a programming signal to the resistance variable memory cell to program the cell to a target state, subsequently applying a pre-read signal to the resistance variable memory cell to accelerate a drift of a resistance of the programmed cell, and subsequently applying a read signal to the resistance variable memory cell.

公开(公告)号：US20160372193A1

公开(公告)日：2016-12-22

申请号：US15180556

申请日：2016-06-13

Applicant: Intel Corporation

Inventor： Arjun Kripanidhi ,  Kiran Pangal ,  Lark-Hoon Leem ,  Balaji Srinivasan

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0052 ,  G11C2013/0066

Abstract: Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了在相变存储器中的读取和写入操作以减少突发干扰。 在一个实施例中，一种装置包括读取电路，用于将读取电压施加到相变存储器（PCM）单元，响应于读取电压的应用，将回退脉冲施加到PCM单元，其中挫折脉冲是 对于被配置为将PCM单元从非晶状态转换为结晶状态的规则设定脉冲，对于比第二时间段短的第一时间段执行的更短的设定脉冲，感测电路与应用同时感测 的挫折脉冲，PCM单元是处于非晶态还是结晶状态。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160284398A1

公开(公告)日：2016-09-29

申请号：US14671471

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Arjun Kripanidhi ,  Kiran Pangal ,  Lark-Hoon Leem ,  Balaji Srinivasan

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0052 ,  G11C2013/0066

Abstract: Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed.

公开(公告)号：US09455011B2

公开(公告)日：2016-09-27

申请号：US14350997

申请日：2012-03-25

Applicant: Arijit Raychowdhury ,  David Kencke ,  Brian Doyle ,  Charles Kuo ,  James Tschanz ,  Fatih Hamzaoglu ,  Yih Wang ,  Roksana Golizadeh Mojarad

Inventor： Arijit Raychowdhury ,  David Kencke ,  Brian Doyle ,  Charles Kuo ,  James Tschanz ,  Fatih Hamzaoglu ,  Yih Wang ,  Roksana Golizadeh Mojarad

IPC: G11C11/00 ,  G11C11/16 ,  G11C5/12 ,  G11C13/00

CPC classification number: G11C11/165 ,  G11C5/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0052 ,  G11C2013/0071

Abstract: Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.

Abstract translation: 基于脉冲读取电流读取存储在基于磁隧道结（MTJ）的存储单元中的逻辑值的方法和系统，脉冲之间的时间允许MTJ朝向脉冲之间的磁化取向松弛，这可以减少构建 - MTJ内的动量，并且其可以减少和/或消除磁化取向的无意重新对准。 对称和/或非对称脉冲的序列可以被施加到字线（WL），以使预充电位线（BL）电容放电通过MTJ的脉冲读取电流，从而产生相应的电压变化序列 在BL上。 可以在读取电流脉冲的序列上积分BL电压变化，并且可以基于积分的电压变化来确定存储的逻辑值。 预充电的BL电容也可以用作电压积分器。

公开(公告)号：US20160133308A1

公开(公告)日：2016-05-12

申请号：US14988144

申请日：2016-01-05

Applicant: Katsuyuki FUJITA

Inventor： Katsuyuki FUJITA

IPC: G11C11/16 ,  G11C29/44

CPC classification number: G11C11/1675 ,  G06F11/00 ,  G06F11/3037 ,  G06F11/3058 ,  G11C7/04 ,  G11C7/08 ,  G11C7/1006 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/5607 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/26 ,  G11C29/44 ,  G11C2013/0052 ,  G11C2013/0092 ,  G11C2029/0411

Abstract: A resistance change memory includes a memory cell array comprising memory cells including magnetic tunnel junction (MTJ) elements; a write and read circuit which performs a write operation and a read operation for the memory cells; a temperature sensor which outputs temperature information corresponding to a temperature of the memory cell array; and a memory controller which controls the write operation and the read operation by the write and read circuit in response to the temperature information, such that a first time period from a write command input to a pre-charge command input is variable according to the temperature information, while a second time period from an active command input to the pre-charge command input is fixed constant regardless of the temperature information.

Abstract translation: 电阻变化存储器包括存储单元阵列，其包括包括磁性隧道结（MTJ）元件的存储单元; 写入和读取电路，用于对存储器单元执行写入操作和读取操作; 温度传感器，其输出与存储单元阵列的温度对应的温度信息; 以及存储器控制器，其响应于温度信息控制写入和读取电路的写入操作和读取操作，使得从写入命令输入到预充电命令输入的第一时间段根据温度而变化 信息，而从活动命令输入到预充电命令输入的第二时间段不管温度信息如何都是固定的。

公开(公告)号：US20160104530A1

公开(公告)日：2016-04-14

申请号：US14970911

申请日：2015-12-16

Applicant: Micron Technology, Inc.

Inventor： Alessandro Calderoni ,  Massimo Ferro ,  Paolo Fantini

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/00 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/0069 ,  G11C13/0097 ,  G11C29/006 ,  G11C29/50008 ,  G11C2013/0052 ,  G11C2013/0057

Abstract: The present disclosure includes apparatuses and methods including drift acceleration in resistance variable memory. A number of embodiments include applying a programming signal to the resistance variable memory cell to program the cell to a target state, subsequently applying a pre-read signal to the resistance variable memory cell to accelerate a drift of a resistance of the programmed cell, and subsequently applying a read signal to the resistance variable memory cell.

公开(公告)号：US09251895B2

公开(公告)日：2016-02-02

申请号：US14512545

申请日：2014-10-13

Applicant: Ovonyx, Inc.

Inventor： George A. Gordon ,  Semyon D. Savransky ,  Ward D. Parkinson ,  Sergey Kostylev ,  James Reed ,  Tyler A. Lowrey ,  Ilya V. Karpov ,  Gianpaolo Spadini

IPC: G11C29/00 ,  G11C13/00 ,  G11C8/10 ,  G11C11/56 ,  G11C16/34 ,  G11C29/04

CPC classification number: G11C13/0033 ,  G11C8/10 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/3431 ,  G11C29/04 ,  G11C2013/0052 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/76

Abstract: Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb.