公开(公告)号：US20220093741A1

公开(公告)日：2022-03-24

申请号：US17511579

申请日：2021-10-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Hsu ,  Chin-Hung Chen ,  Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Tsai-Yu Wen ,  Shi You Liu ,  Yu-Hsiang Lin

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/06 ,  H01L29/167

Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.

公开(公告)号：US11107689B2

公开(公告)日：2021-08-31

申请号：US16207201

申请日：2018-12-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ming-Shiou Hsieh ,  Rong-Sin Lin ,  Ching-I Li ,  Neng-Hui Yang

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.

公开(公告)号：US09947588B1

公开(公告)日：2018-04-17

申请号：US15817274

申请日：2017-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Neng-Hui Yang ,  Tsai-Yu Wen ,  Ching-I Li

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/823431 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/265 ,  H01L21/324 ,  H01L21/823468 ,  H01L21/823481

Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

公开(公告)号：US09735235B2

公开(公告)日：2017-08-15

申请号：US15215609

申请日：2016-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Chin-Sheng Yang ,  Chun-Jen Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/306 ,  H01L29/161 ,  H01L21/316 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/0673 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02603 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

公开(公告)号：US09685533B1

公开(公告)日：2017-06-20

申请号：US15049133

申请日：2016-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Po-Jen Chuang ,  Fu-Jung Chuang ,  Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Fu-Yu Tsai

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/49 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, agate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.

公开(公告)号：US20140295629A1

公开(公告)日：2014-10-02

申请号：US13850887

申请日：2013-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Hsin-Kuo Hsu ,  Yu-Shu Lin ,  Szu-Hao Lai ,  Ming-Hua Chang

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  Y10S438/938

Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.

Abstract translation: 公开了一种形成半导体器件的方法。 至少一个栅极结构设置在衬底上，其中栅极结构包括形成在栅极的侧壁上的第一间隔物。 在覆盖栅极结构的衬底上沉积第一一次性间隔物层。 第一一次性间隔物材料层被蚀刻以在第一间隔物上形成第一一次性间隔物。 在覆盖栅极结构的衬底上沉积第二一次性间隔物材料层。 蚀刻第二一次性间隔材料层以在第一一次性间隔件上形成第二一次性间隔件。 通过使用第一和第二一次性间隔件作为掩模来去除衬底的一部分，以在栅极结构旁边的衬底中形成两个凹部。 在凹部中形成应力诱导层。

公开(公告)号：US11791413B2

公开(公告)日：2023-10-17

申请号：US17392222

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Shih-Cheng Chen ,  Chia-Wei Chang ,  Chia-Ming Kuo ,  Tsai-Yu Wen ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L23/10

CPC classification number: H01L29/7851 ,  H01L21/02126 ,  H01L23/10 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66795

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.

公开(公告)号：US20230014253A1

公开(公告)日：2023-01-19

申请号：US17392222

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Shih-Cheng Chen ,  Chia-Wei Chang ,  Chia-Ming Kuo ,  Tsai-Yu Wen ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L23/10

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.

公开(公告)号：US11271078B2

公开(公告)日：2022-03-08

申请号：US16836953

申请日：2020-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

公开(公告)号：US20170243952A1

公开(公告)日：2017-08-24

申请号：US15592150

申请日：2017-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Po-Jen Chuang ,  Fu-Jung Chuang ,  Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Fu-Yu Tsai

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, agate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.