公开(公告)号：US11107689B2

公开(公告)日：2021-08-31

申请号：US16207201

申请日：2018-12-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ming-Shiou Hsieh ,  Rong-Sin Lin ,  Ching-I Li ,  Neng-Hui Yang

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.

公开(公告)号：US10332750B2

公开(公告)日：2019-06-25

申请号：US15820443

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Hsu Ting ,  Chung-Fu Chang ,  Shi-You Liu ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L21/3105 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/165 ,  H01L21/266 ,  H01L21/324 ,  H01L29/08

Abstract: A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.

公开(公告)号：US09947588B1

公开(公告)日：2018-04-17

申请号：US15817274

申请日：2017-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Neng-Hui Yang ,  Tsai-Yu Wen ,  Ching-I Li

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/823431 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/265 ,  H01L21/324 ,  H01L21/823468 ,  H01L21/823481

Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

公开(公告)号：US20170330937A1

公开(公告)日：2017-11-16

申请号：US15632399

申请日：2017-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Yi-Wei Chen ,  I-Cheng Hu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/36 ,  H01L29/167 ,  H01L29/165 ,  H01L21/265 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/324 ,  H01L21/283 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53252 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

公开(公告)号：US20220140080A1

公开(公告)日：2022-05-05

申请号：US17580622

申请日：2022-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US20200235208A1

公开(公告)日：2020-07-23

申请号：US16836953

申请日：2020-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

公开(公告)号：US20190067477A1

公开(公告)日：2019-02-28

申请号：US15688824

申请日：2017-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Ming-Shiou Hsieh ,  Rong-Sin Lin ,  Han-Ting Yen ,  Tsai-Yu Wen ,  Ching-I Li

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

Abstract: A semiconductor structure includes a substrate, fin-shaped structures disposed on the substrate, an isolation layer disposed between the fin-shaped structures, and a doped region disposed in an upper portion of the isolation layer, where the doped region is doped with helium or neon.

公开(公告)号：US09966434B2

公开(公告)日：2018-05-08

申请号：US15632399

申请日：2017-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Yi-Wei Chen ,  I-Cheng Hu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/165 ,  H01L29/36 ,  H01L21/265 ,  H01L21/324 ,  H01L29/167 ,  H01L21/283 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53252 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

公开(公告)号：US11664425B2

公开(公告)日：2023-05-30

申请号：US17580622

申请日：2022-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

CPC classification number: H01L29/105 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26533 ,  H01L21/324 ,  H01L21/823412 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US10700202B2

公开(公告)日：2020-06-30

申请号：US16172856

申请日：2018-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Sung-Yuan Tsai ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Chao-Nan Chen ,  Shi-You Liu ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.