公开(公告)号：US20220181505A1

公开(公告)日：2022-06-09

申请号：US17145416

申请日：2021-01-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Li Lin ,  Wei-Da Lin ,  Cheng-Guo Chen ,  Ta-Kang Lo ,  Yi-Chuan Chen ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Kuan-Ting Lu ,  Kuo-Yu Liao

IPC: H01L29/94 ,  H01L29/66

Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

公开(公告)号：US11664425B2

公开(公告)日：2023-05-30

申请号：US17580622

申请日：2022-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

CPC classification number: H01L29/105 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26533 ,  H01L21/324 ,  H01L21/823412 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US10651275B2

公开(公告)日：2020-05-12

申请号：US15893681

申请日：2018-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US20190214465A1

公开(公告)日：2019-07-11

申请号：US15893681

申请日：2018-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US11916126B2

公开(公告)日：2024-02-27

申请号：US17989710

申请日：2022-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Hsin Hsu ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Shih-Min Chou ,  Nien-Ting Ho ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.

公开(公告)号：US20230078993A1

公开(公告)日：2023-03-16

申请号：US17989710

申请日：2022-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Hsin Hsu ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Shih-Min Chou ,  Nien-Ting Ho ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.

公开(公告)号：US11271078B2

公开(公告)日：2022-03-08

申请号：US16836953

申请日：2020-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

公开(公告)号：US20240243185A1

公开(公告)日：2024-07-18

申请号：US18171293

申请日：2023-02-17

Applicant: United Microelectronics Corp.

Inventor： Huan Chi Ma ,  Kuan-Ting Lin ,  Ying Jie Huang ,  Chien-Wen Yu

IPC: H01L29/66 ,  H01L21/225 ,  H01L21/311 ,  H01L29/10 ,  H01L29/207 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/2258 ,  H01L21/31116 ,  H01L29/1029 ,  H01L29/207 ,  H01L29/7786 ,  H01L29/2003

Abstract: Provided is a semiconductor device including an enhancement mode (E-mode) high electron mobility transistor (HEMT). The E-mode HEMT includes a substrate, and a channel layer disposed on the substrate. A barrier structure disposed on the channel layer. A pair of source/drain (S/D) metals respectively disposed on the channel layer at opposite sides of the barrier structure. A gate metal disposed on the barrier structure between the pair of S/D metals. The channel layer has a two-dimensional electron gas (2DEG) layer close to an interface between the channel layer and the barrier structure. A fluorine ion concentration in the channel layer adjacent to the 2DEG layer is greater than that away from the 2DEG layer.

公开(公告)号：US20230048684A1

公开(公告)日：2023-02-16

申请号：US17976888

申请日：2022-10-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Li Lin ,  Wei-Da Lin ,  Cheng-Guo Chen ,  Ta-Kang Lo ,  Yi-Chuan Chen ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Kuan-Ting Lu ,  Kuo-Yu Liao

IPC: H01L29/94 ,  H01L29/66

Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

公开(公告)号：US11538917B2

公开(公告)日：2022-12-27

申请号：US17353830

申请日：2021-06-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Hsin Hsu ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Shih-Min Chou ,  Nien-Ting Ho ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer and a titanium aluminide layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and a thickness of the titanium aluminide layer ranges from twice a thickness of the titanium nitride barrier layer to three times the thickness of the titanium nitride barrier layer.