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    CHIP PACKAGE INCORPORATING INTERFACIAL ADHESION THROUGH CONDUCTOR SPUTTERING
    1.
    发明申请
    CHIP PACKAGE INCORPORATING INTERFACIAL ADHESION THROUGH CONDUCTOR SPUTTERING 有权
    通过导线溅射引入界面粘合剂的芯片包装

    公开(公告)号：US20150021778A1

    公开(公告)日：2015-01-22

    申请号：US14506357

    申请日：2014-10-03

    申请人： Tao Wu ,  Islam A. Salama

    发明人： Tao Wu ,  Islam A. Salama

    IPC分类号： H01L23/522 ,  H01L23/532

    CPC分类号： H01L23/5226 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/48 ,  H01L23/525 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line.

    摘要翻译： 本公开一般涉及可以包括制造芯片封装的方法的电子设备和方法。 1.一种绝缘体层，包括绝缘体材料，所述绝缘体层相对于第一导电线定位，相对于所述绝缘体层形成第二导电线，其中所述绝缘体层位于所述第一导电线和所述第二导电线之间，形成 所述绝缘体层在所述第一导电线和所述第二导电线之间的开口，所述开口内的所述绝缘体材料中的至少一些被暴露，以及将导体化学键合到所述开口内的所述至少一些所述绝缘体材料，其中， 导体将第一导线电耦合到第二导线。

    SUBSTRATE CORES FOR LASER THROUGH HOLE FORMATION
    3.
    发明申请
    SUBSTRATE CORES FOR LASER THROUGH HOLE FORMATION 审中-公开
    通过孔形成激光的基底线

    公开(公告)号：US20140004361A1

    公开(公告)日：2014-01-02

    申请号：US13536709

    申请日：2012-06-28

    申请人： Nikhil Sharma ,  Chong Zhang ,  Tao Wu ,  Islam A. Salama

    发明人： Nikhil Sharma ,  Chong Zhang ,  Tao Wu ,  Islam A. Salama

    IPC分类号： B32B27/02 ,  B23K26/38

    CPC分类号： B32B27/02 ,  B23K26/382 ,  B23K26/40 ,  B23K2103/172 ,  Y10T428/31855

    摘要： Substrate cores for laser through hole formation are described. Substrate core embodiments include a plurality of reinforcement material layers and a microfiller loaded resin disposed between the plurality of reinforcement material layers. Microfiller and reinforcement materials are selected to reduce opto-thermal mismatch for a laser of a predetermined bandwidth. In embodiments, the reinforcement material may include a fibrous polymer, reducing the thermal contrast with the microfiller loaded resin, and/or include a chromophore that absorbs within the laser bandwidth. In further embodiments, the microfiller is of a material having a high melting temperature to reduce thermal contrast with the reinforcement material.

    摘要翻译： 描述了用于激光通孔形成的基板芯。 基底芯实施例包括多个增强材料层和设置在多个增强材料层之间的装载有微粒填料的树脂。 选择微型填充物和增强材料以减少预定带宽的激光器的光热失配。 在实施方案中，增强材料可以包括纤维聚合物，减少与填充微粒填料的树脂的热对比度，和/或包括在激光带宽内吸收的发色团。 在另外的实施方案中，微细粉末是具有高熔融温度以减少与增强材料的热对比度的材料。

    Chip package incorporating interfacial adhesion through conductor sputtering
    4.
    发明授权
    Chip package incorporating interfacial adhesion through conductor sputtering 有权
    通过导体溅射结合界面粘合的芯片封装

    公开(公告)号：US08871634B2

    公开(公告)日：2014-10-28

    申请号：US13599411

    申请日：2012-08-30

    申请人： Tao Wu ,  Islam A. Salama

    发明人： Tao Wu ,  Islam A. Salama

    IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/48

    CPC分类号： H01L23/5226 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/48 ,  H01L23/525 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line.

    摘要翻译： 本公开一般涉及可以包括制造芯片封装的方法的电子设备和方法。 1.一种绝缘体层，包括绝缘体材料，所述绝缘体层相对于第一导电线定位，相对于所述绝缘体层形成第二导电线，其中所述绝缘体层位于所述第一导电线和所述第二导电线之间，形成 所述绝缘体层在所述第一导电线和所述第二导电线之间的开口，所述开口内的所述绝缘体材料中的至少一些被暴露，以及将导体化学键合到所述开口内的所述至少一些所述绝缘体材料，其中， 导体将第一导线电耦合到第二导线。

    CHIP PACKAGE INCORPORATING INTERFACIAL ADHESION THROUGH CONDUCTOR SPUTTERING
    5.
    发明申请
    CHIP PACKAGE INCORPORATING INTERFACIAL ADHESION THROUGH CONDUCTOR SPUTTERING 有权
    通过导线溅射引入界面粘合剂的芯片包装

    公开(公告)号：US20140061927A1

    公开(公告)日：2014-03-06

    申请号：US13599411

    申请日：2012-08-30

    申请人： Tao Wu ,  Islam A. Salama

    发明人： Tao Wu ,  Islam A. Salama

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L23/5226 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/48 ,  H01L23/525 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line.

    摘要翻译： 本公开一般涉及可以包括制造芯片封装的方法的电子设备和方法。 1.一种绝缘体层，包括绝缘体材料，所述绝缘体层相对于第一导电线定位，相对于所述绝缘体层形成第二导电线，其中所述绝缘体层位于所述第一导电线和所述第二导电线之间，形成 所述绝缘体层在所述第一导电线和所述第二导电线之间的开口，所述开口内的所述绝缘体材料中的至少一些被暴露，以及将导体化学键合到所述开口内的所述至少一些所述绝缘体材料，其中， 导体将第一导线电耦合到第二导线。

    PACKAGE ASSEMBLY CONFIGURATIONS FOR MULTIPLE DIES AND ASSOCIATED TECHNIQUES
    7.
    发明申请
    PACKAGE ASSEMBLY CONFIGURATIONS FOR MULTIPLE DIES AND ASSOCIATED TECHNIQUES 审中-公开
    多组合和相关技术的封装组装配置

    公开(公告)号：US20150014852A1

    公开(公告)日：2015-01-15

    申请号：US13941322

    申请日：2013-07-12

    申请人： Yueli Liu ,  Islam A. Salama ,  Mihir K. Roy ,  Ram S. Viswanath

    发明人： Yueli Liu ,  Islam A. Salama ,  Mihir K. Roy ,  Ram S. Viswanath

    IPC分类号： H01L23/498 ,  H01L23/00

    CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00

    摘要： Embodiments of the present disclosure are directed towards package assembly configurations for multiple dies and associated techniques. In one embodiment, a package assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die mounted on the first side and electrically coupled with the package substrate by one or more first die-level interconnects, a second die mounted on the second side and electrically coupled with the package substrate by one or more second die-level interconnects and package-level interconnect structures disposed on the first side of the package substrate and configured to route electrical signals between the first die and an electrical device external to the package substrate and between the second die and the external device. Other embodiments may be described and/or claimed.

    摘要翻译： 本公开的实施例涉及用于多个管芯和相关技术的封装组装构造。 在一个实施例中，封装组件包括具有第一侧和与第一侧相对设置的第二侧的封装衬底，第一裸片安装在第一侧上并且通过一个或多个第一裸片级互连与封装衬底电耦合 ，安装在所述第二侧上的第二裸片，并且通过设置在所述封装衬底的所述第一侧上的一个或多个第二管芯级互连和封装级互连结构与所述封装衬底电耦合，并且被配置为将所述第一管芯 以及在封装衬底外部以及第二管芯和外部器件之间的电器件。 可以描述和/或要求保护其他实施例。

    PACKAGE SUBSTRATE WITH HIGH DENSITY INTERCONNECT DESIGN TO CAPTURE CONDUCTIVE FEATURES ON EMBEDDED DIE
    8.
    发明申请
    PACKAGE SUBSTRATE WITH HIGH DENSITY INTERCONNECT DESIGN TO CAPTURE CONDUCTIVE FEATURES ON EMBEDDED DIE 有权
    具有高密度互连设计的封装基板，用于捕获嵌入式电源的导电特性

    公开(公告)号：US20140321091A1

    公开(公告)日：2014-10-30

    申请号：US13870874

    申请日：2013-04-25

    申请人： Chong Zhang ,  Stefanie M. Lotz ,  Islam A. Salama

    发明人： Chong Zhang ,  Stefanie M. Lotz ,  Islam A. Salama

    IPC分类号： H05K1/11 ,  H05K3/40

    CPC分类号： H05K1/115 ,  H01L23/5385 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/185 ,  H05K3/10 ,  H05K3/4007 ,  H05K3/4084 ,  H05K2201/10363 ,  H01L2924/00

    摘要： Embodiments of the present disclosure are directed towards techniques and configurations for interconnect structures embedded in a package assembly including a bridge. In one embodiment, a package assembly may include a package substrate, a bridge embedded in the package substrate and including a bridge substrate, and an interconnect structure including a via extending through the package substrate into a surface of the bridge substrate and configured to interface with a conductive feature disposed on or beneath the surface of the bridge substrate. The interconnect structure may be configured to route electrical signals between the conductive feature and a die mounted on the package substrate. Other embodiments may be described and/or claimed.

    摘要翻译： 本公开的实施例涉及嵌入在包括桥的包装组件中的互连结构的技术和配置。 在一个实施例中，封装组件可以包括封装衬底，嵌入在封装衬底中并包括桥接衬底的桥，以及互连结构，其包括延伸穿过封装衬底进入桥接衬底的表面的通孔，并且被配置为与 导电特征设置在桥基板的表面上或下方。 互连结构可以被配置为在导电特征和安装在封装衬底上的管芯之间布置电信号。 可以描述和/或要求保护其他实施例。

    Optical device and method of making
    10.
    发明授权
    Optical device and method of making 有权

    公开(公告)号：US07951632B1

    公开(公告)日：2011-05-31

    申请号：US11340883

    申请日：2006-01-26

    申请人： Nathaniel R. Quick ,  Aravinda Kar ,  Islam A. Salama

    发明人： Nathaniel R. Quick ,  Aravinda Kar ,  Islam A. Salama

    IPC分类号： H01L21/268

    CPC分类号： H01L21/268 ,  G01J5/08 ,  G01J5/0809 ,  G01J5/58 ,  G01K11/125 ,  H01L21/02678

    摘要： An optical device and method is disclosed for forming the optical device within the wide-bandgap semiconductor substrate. The optical device is formed by directing a thermal energy beam onto a selected portion of the wide-bandgap semiconductor substrate for changing an optical property of the selected portion to form the optical device in the wide-bandgap semiconductor substrate. The thermal energy beam defines the optical and physical properties of the optical device. The optical device may take the form of an electro-optical device with the addition of electrodes located on the wide-bandgap semiconductor substrate in proximity to the optical device for changing the optical property of the optical device upon a change of a voltage applied to the optional electrodes. The invention is also incorporated into a method of using the optical device for remotely sensing temperature, pressure and/or chemical composition.