公开(公告)号：US20250095702A1

公开(公告)日：2025-03-20

申请号：US18967733

申请日：2024-12-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih ,  Jonathan Tsung-Yung Chang

IPC: G11C7/12 ,  G11C5/06 ,  G11C7/10 ,  G11C16/04 ,  G11C16/30

Abstract: Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.

公开(公告)号：US12248331B2

公开(公告)日：2025-03-11

申请号：US17877115

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Chin-I Su

IPC: G05F1/575 ,  G05F1/565

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

公开(公告)号：US20240407159A1

公开(公告)日：2024-12-05

申请号：US18326228

申请日：2023-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih ,  Ya-Chin King ,  Chrong Lin ,  Jonathan Tsung-Yung Chang ,  Yun-Sheng Chen ,  May-Be Chen ,  Hsin-Yuan Yu

IPC: H10B20/25

Abstract: A memory device is disclosed. The memory device includes a memory cell comprising: a transistor; and a plurality of pairs of resistors coupled to the transistor in series, each of the pairs of resistors including a first resistor and a second resistor. The transistor is formed along a major surface of a substrate. At least a first one of the pairs of resistors are formed in a first one of a plurality of metallization layers disposed above the transistor. At least a second one of the pairs of resistors are formed in a second one of the plurality of metallization layers, the second metallization layer being disposed above the first metallization layer.

公开(公告)号：US20240347090A1

公开(公告)日：2024-10-17

申请号：US18635929

申请日：2024-04-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Po-Hao Lee ,  Ku-Feng Lin ,  Yi-Chun Shih ,  Yu-Der Chih

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  H10B61/22 ,  H10N50/10

Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

公开(公告)号：US11984162B2

公开(公告)日：2024-05-14

申请号：US17981977

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Pei-Ling Tseng

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0064 ,  G11C13/003 ,  G11C13/004

Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.

公开(公告)号：US20240036597A1

公开(公告)日：2024-02-01

申请号：US17877115

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Chin-I Su

IPC: G05F1/575 ,  G05F1/565

CPC classification number: G05F1/575 ,  G05F1/565

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

公开(公告)号：US11791006B2

公开(公告)日：2023-10-17

申请号：US17816118

申请日：2022-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Gu-Huan Li ,  Chen-Ming Hung ,  Yu-Der Chih

IPC: G11C17/18 ,  G11C17/16 ,  G11C8/10 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C17/18 ,  G11C7/1069 ,  G11C7/1096 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4099 ,  G11C17/16

Abstract: A memory circuit includes a bank of non-volatile memory (NVM) devices, a plurality of high-voltage (HV) drivers, a global HV power switch configured to generate a HV power signal, and a plurality of HV power switches coupled to the global HV switch. A first HV power switch of the plurality of HV power switches is coupled to each HV driver of the plurality of HV drivers, the first HV power switch of the plurality of HV power switches is configured to output a power signal responsive to the HV power signal, and each HV driver of the plurality of HV drivers is configured to output a HV activation signal to a corresponding column of the bank of NVM devices responsive to the power signal.

公开(公告)号：US20230317159A1

公开(公告)日：2023-10-05

申请号：US17709662

申请日：2022-03-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih ,  Chung-Cheng Chou ,  Chun-Yun Wu ,  Chen-Ming Hung

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C13/004 ,  G11C13/0028 ,  G11C13/0026 ,  G11C13/0038

Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.

公开(公告)号：US11735263B2

公开(公告)日：2023-08-22

申请号：US17871144

申请日：2022-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chin-I Su ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Zheng-Jun Lin

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0028 ,  G11C13/0038 ,  G11C2013/0078 ,  G11C2213/79

Abstract: A method of operating a memory circuit includes generating a first voltage by a first amplifier circuit of a first driver circuit coupled to a first column of memory cells, and generating a first current in response to the first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.

公开(公告)号：US20230197122A1

公开(公告)日：2023-06-22

申请号：US18168226

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C11/16 ,  G11C29/42

CPC classification number: G11C7/08 ,  G11C7/067 ,  G11C7/1039 ,  G11C11/1673 ,  G11C29/42

Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.