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    Non-volatile memory circuit and method
    1.
    发明授权
    Non-volatile memory circuit and method 有权

    公开(公告)号：US11450395B2

    公开(公告)日：2022-09-20

    申请号：US17237688

    申请日：2021-04-22

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Gu-Huan Li ,  Chen-Ming Hung ,  Yu-Der Chih

    IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16 ,  G11C8/10 ,  G11C7/10

    Abstract: A memory circuit includes a first bank of non-volatile memory (NVM) devices, a first plurality of decoders, a first plurality of high-voltage (HV) drivers corresponding to the first plurality of decoders, and a first plurality of HV power switches. A first HV power switch is coupled to each HV driver of the first plurality of HV drivers, and each decoder is configured to generate an enable signal corresponding to a column of the first bank of NVM devices. Each HV driver is configured to output a HV activation signal to the corresponding column of the first bank of NVM devices responsive to a power signal of the first HV power switch and to the enable signal of the corresponding decoder.

    Anti-fuse array
    2.
    发明授权
    Anti-fuse array 有权

    公开(公告)号：US12073169B2

    公开(公告)日：2024-08-27

    申请号：US18446684

    申请日：2023-08-09

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Meng-Sheng Chang ,  Shao-Yu Chou ,  Yao-Jen Yang ,  Chen-Ming Hung

    IPC: G06F7/50 ,  G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/528 ,  H10B20/20 ,  H01L23/525

    CPC classification number: G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/528 ,  H10B20/20 ,  H01L23/5252

    Abstract: An anti-fuse array includes first through fourth adjacent anti-fuse bit columns, the anti-fuse bits of the first and second anti-fuse bit columns including portions of active areas of a first active area column, and the anti-fuse bits of the third and fourth anti-fuse bit columns including portions of active areas of a second active area column. Each row of a first set of conductive segment rows includes first and second conductive segments positioned between adjacent active areas of the first active area column and a third conductive segment positioned between adjacent active areas of the second active area column. Each row of a second set of conductive segments alternating with the first set of conductive segment rows includes a fourth conductive segment positioned between adjacent active areas of the first active area column and fifth and sixth conductive segments positioned between adjacent active areas of the second active area column.

    Generating stabilized output signals during fuse read operations
    7.
    发明授权
    Generating stabilized output signals during fuse read operations 有权
    在保险丝读取操作期间产生稳定的输出信号

    公开(公告)号：US09558841B2

    公开(公告)日：2017-01-31

    申请号：US13918681

    申请日：2013-06-14

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Sung-Chieh Lin ,  Kuo-Yuan Hsu ,  Wei-Li Liao ,  Chen-Ming Hung ,  Yun-Han Chen ,  Shao-Cheng Wang

    IPC: G11C17/16 ,  G11C17/18

    CPC classification number: G11C17/16 ,  G11C17/18

    Abstract: A circuit includes a fuse cell, a sense circuit and an output control circuit. The fuse cell includes an electrical fuse. The sense circuit is electrically coupled to the fuse cell and configured for generating a sense signal indicative of a programmed condition of the electrical fuse, at an output of the sense circuit. The output control circuit is electrically coupled to the output of the sense circuit, and the output control circuit is configured for latching the sense signal indicative of the electrical fuse having been programmed, during a read operation of the fuse cell.

    Abstract translation: 电路包括熔丝单元，感测电路和输出控制电路。 保险丝盒包括电熔丝。 感测电路电耦合到熔丝单元并且被配置为在感测电路的输出处产生指示电熔丝的编程状态的感测信号。 输出控制电路电耦合到感测电路的输出，并且输出控制电路被配置为在熔丝单元的读取操作期间锁存指示已经编程的电熔丝的感测信号。

    VOLTAGE REGULATORS WITH SHARED DECOUPLING CAPACITOR FOR MEMORY DEVICES
    8.
    发明申请
    VOLTAGE REGULATORS WITH SHARED DECOUPLING CAPACITOR FOR MEMORY DEVICES 有权

    公开(公告)号：US20240411334A1

    公开(公告)日：2024-12-12

    申请号：US18331620

    申请日：2023-06-08

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Zheng-Jun Lin ,  Chen-Ming Hung ,  Chung-Cheng Chou

    IPC: G05F1/59 ,  G11C11/16 ,  G11C13/00

    Abstract: A circuit includes a memory macro comprising a plurality of memory banks. The circuit includes a first voltage regulator configured to provide a first operation voltage to the memory macro at a first output node. The circuit includes a second voltage regulator configured to provide a second operation voltage to the memory macro at a second output node. The second operation voltage is substantially higher than the first operation voltage. The circuit includes a decoupling capacitor configured to be alternately shared by the first voltage regulator when the memory macro receives the first operation voltage, and by the second voltage regulator when the memory macro receives the second operation voltage.

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