PRE-CLEANING FOR A DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR

    公开(公告)号:US20230378215A1

    公开(公告)日:2023-11-23

    申请号:US17663801

    申请日:2022-05-17

    IPC分类号: H01L27/146 H01L21/306

    摘要: A cyclic pre-cleaning technique may be used to clean the surfaces of a recess in which a deep trench isolation (DTI) structure is to be formed. The cyclic pre-cleaning technique may include performing one or more deposition and etch cycles to remove oxygen from the surfaces of the recess to reduce the oxygen concentration in the surfaces of the recess. A passivation layer may be formed in the recess after the cyclic pre-cleaning technique is used to clean the surfaces. The cyclic pre-cleaning technique may include the use of germanium (Ge) to bond with oxygen in the surfaces of the recess, which results in the formation of germanium oxide (GeO). The germanium oxide is removed, resulting in reduced oxygen concentration in the surfaces of the recess. The reduced oxygen concentration increases the quality of epitaxial growth of the passivation layer in the recess.

    TRAPPING LAYER FOR A RADIO FREQUENCY DIE AND METHODS OF FORMATION

    公开(公告)号:US20240030222A1

    公开(公告)日:2024-01-25

    申请号:US17869135

    申请日:2022-07-20

    摘要: An insulator layer of a trap-rich silicon-on-insulator (SOI) wafer is formed on a trapping layer over a high-temperature substrate instead of forming the insulator layer on a bulk silicon substrate. The silicon layer of the trap-rich SOI wafer is formed on a second wafer and is bonded to the insulator layer that was grown on the trapping layer. The second wafer is then removed by grinding, polishing, and/or another technique such that no cutting of the silicon device layer is performed, and therefore little to no surface damage is caused to the silicon layer. Accordingly, a high-temperature annealing operation to remove surface damage that would otherwise be caused by cutting of the silicon layer may be omitted. Thus, operations to form the trap-rich SOI wafer may be performed at lower temperatures, which enables the trapping layer of the trap-rich SOI wafer to be formed to a lesser thickness.

    STRAINED SEMICONDUCTOR DEVICE WITH FACETS
    9.
    发明申请
    STRAINED SEMICONDUCTOR DEVICE WITH FACETS 有权
    应变半导体器件与面

    公开(公告)号:US20130244389A1

    公开(公告)日:2013-09-19

    申请号:US13889846

    申请日:2013-05-08

    IPC分类号: H01L29/66

    摘要: A method for fabricating a semiconductor device, the method includes forming a gate stack over a major surface of a substrate. The method further includes recessing the substrate to form source and drain recess cavities adjacent to the gate stack in the substrate. The method further includes selectively growing a strained material in the source and drain recess cavities in the substrate using an LPCVD process, wherein the LPCVD process is performed at a temperature of about 660 to 700° C. and under a pressure of about 13 to 50 Torr, using SiH2Cl2, HCl, GeH4, B2H6, and H2 as reaction gases.

    摘要翻译: 一种制造半导体器件的方法,所述方法包括在衬底的主表面上形成栅叠层。 该方法还包括使衬底凹陷以形成与衬底中的栅极堆叠相邻的源极和漏极凹腔。 该方法还包括使用LPCVD工艺选择性地生长衬底中的源极和漏极凹腔中的应变材料,其中LPCVD工艺在约660-700℃的温度和约13至50℃的压力下进行 Torr,使用SiH2Cl2,HCl,GeH4,B2H6和H2作为反应气体。