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公开(公告)号:US20240072082A1
公开(公告)日:2024-02-29
申请号:US17822600
申请日:2022-08-26
发明人: Yu-Hung CHENG , Tzu-Jui WANG , Ching I. LI
IPC分类号: H01L27/146
CPC分类号: H01L27/14614 , H01L27/14621 , H01L27/14627 , H01L27/1463 , H01L27/14645 , H01L27/14689 , H01L27/14698
摘要: A boron (B) layer may be formed as a passivation layer in a recess in which a vertical transfer gate is to be formed. The recess may then be filled with a gate electrode of the vertical transfer gate over the passivation layer (and/or one or more intervening layers) to form the vertical transfer gate. The passivation layer may be formed in the recess by epitaxial growth. The use of epitaxy to grow the passivation layer enables precise control over the profile, uniformity, and boron concentration in the passivation layer. Moreover, the use of epitaxy to grow the passivation layer may reduce the diffusion length of the passivation layer into the substrate of the pixel sensor, which provides increased area in the pixel sensor for the photodiode.
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公开(公告)号:US20230378215A1
公开(公告)日:2023-11-23
申请号:US17663801
申请日:2022-05-17
发明人: Yu-Hung CHENG , Yu-Siang FANG , Ching I LI
IPC分类号: H01L27/146 , H01L21/306
CPC分类号: H01L27/1463 , H01L21/30604 , H01L27/14689
摘要: A cyclic pre-cleaning technique may be used to clean the surfaces of a recess in which a deep trench isolation (DTI) structure is to be formed. The cyclic pre-cleaning technique may include performing one or more deposition and etch cycles to remove oxygen from the surfaces of the recess to reduce the oxygen concentration in the surfaces of the recess. A passivation layer may be formed in the recess after the cyclic pre-cleaning technique is used to clean the surfaces. The cyclic pre-cleaning technique may include the use of germanium (Ge) to bond with oxygen in the surfaces of the recess, which results in the formation of germanium oxide (GeO). The germanium oxide is removed, resulting in reduced oxygen concentration in the surfaces of the recess. The reduced oxygen concentration increases the quality of epitaxial growth of the passivation layer in the recess.
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公开(公告)号:US20230369367A1
公开(公告)日:2023-11-16
申请号:US17663108
申请日:2022-05-12
发明人: Yu-Hung CHENG , Yu-Siang FANG , Yu-Yao HSIA , Ching I LI
IPC分类号: H01L27/146
CPC分类号: H01L27/1463 , H01L27/14645 , H01L27/14621 , H01L27/14627 , H01L27/14689 , H01L27/14698
摘要: A boron layer may be formed as a passivation layer in a recess in which a deep trench isolation structure (DTI) structure is to be formed. The boron layer results in formation of a boron-silicon interface between the DTI structure and a photodiode of a pixel sensor included in a pixel array. The boron-silicon interface functions as a diode junction, which resists penetration of photons into the DTI structure. This reduces and/or minimizes photon transmission through the DTI structure, which reduces and/or minimizes optical crosstalk between pixel sensors of the pixel array.
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公开(公告)号:US20200051871A1
公开(公告)日:2020-02-13
申请号:US16658597
申请日:2019-10-21
发明人: Yu-Hung CHENG , Ching-Wei TSAI , Yeur-Luen TU , Tung-I LIN , Wei-Li CHEN
IPC分类号: H01L21/8238 , H01L29/78 , H01L29/66 , H01L27/092
摘要: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.
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公开(公告)号:US20140367768A1
公开(公告)日:2014-12-18
申请号:US14475107
申请日:2014-09-02
发明人: Yen-Ru LEE , Ming-Hua YU , Tze-Liang LEE , Chii-Horng LI , Pang-Yen TSAI , Lilly SU , Yi-Hung LIN , Yu-Hung CHENG
CPC分类号: H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02661 , H01L21/30604 , H01L21/30608 , H01L21/3065 , H01L21/3083 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/66545 , H01L29/66636 , H01L29/7845 , H01L29/7846
摘要: A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution.
摘要翻译: 一种用于制造半导体器件的方法包括在衬底中形成隔离特征,在衬底上形成栅叠层,在衬底中形成源/漏(S / D)凹槽,其中S / D凹腔位于 门堆叠和隔离功能。 该方法还包括在S / D凹陷空腔中形成外延(epi)材料,其中外延材料具有包括第一晶体面的上表面。 另外,该方法包括使用含氯气体对S / D凹腔中的外延材料进行再分配处理,其中第一晶面在再分布之后被转换为第二晶体面。
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公开(公告)号:US20240030222A1
公开(公告)日:2024-01-25
申请号:US17869135
申请日:2022-07-20
发明人: Yu-Hung CHENG , Ching I LI
IPC分类号: H01L27/12 , H01L23/66 , H01L21/762
CPC分类号: H01L27/1207 , H01L23/66 , H01L21/76254 , H01L2223/6616
摘要: An insulator layer of a trap-rich silicon-on-insulator (SOI) wafer is formed on a trapping layer over a high-temperature substrate instead of forming the insulator layer on a bulk silicon substrate. The silicon layer of the trap-rich SOI wafer is formed on a second wafer and is bonded to the insulator layer that was grown on the trapping layer. The second wafer is then removed by grinding, polishing, and/or another technique such that no cutting of the silicon device layer is performed, and therefore little to no surface damage is caused to the silicon layer. Accordingly, a high-temperature annealing operation to remove surface damage that would otherwise be caused by cutting of the silicon layer may be omitted. Thus, operations to form the trap-rich SOI wafer may be performed at lower temperatures, which enables the trapping layer of the trap-rich SOI wafer to be formed to a lesser thickness.
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公开(公告)号:US20180269111A1
公开(公告)日:2018-09-20
申请号:US15982033
申请日:2018-05-17
发明人: Yu-Hung CHENG , Ching-Wei TSAI , Yeur-Luen TU , Tung-I LIN , Wei-Li CHEN
IPC分类号: H01L21/8238 , H01L29/66 , H01L29/78 , H01L27/092
CPC分类号: H01L21/823821 , H01L27/0924 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.
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公开(公告)号:US20160336448A1
公开(公告)日:2016-11-17
申请号:US15223597
申请日:2016-07-29
发明人: Yen-Ru LEE , Ming-Hua YU , Tze-Liang LEE , Chii-Horng LI , Pang-Yen TSAI , Lilly SU , Yi-Hung LIN , Yu-Hung CHENG
IPC分类号: H01L29/78 , H01L21/3065 , H01L21/308 , H01L21/8234 , H01L29/08 , H01L21/02 , H01L29/66 , H01L21/8238 , H01L29/04 , H01L21/306
CPC分类号: H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02661 , H01L21/30604 , H01L21/30608 , H01L21/3065 , H01L21/3083 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/66545 , H01L29/66636 , H01L29/7845 , H01L29/7846
摘要: A method of fabricating a semiconductor device. The method includes forming an isolation feature in a substrate, forming a first gate stack and a second gate stack over the substrate, forming a first recess cavity and a second recess cavity in the substrate, growing a first epitaxial (epi) material in the first recess cavity and a second epi material in the second recess cavity, and etching the first epi material and the second epi material. The first recess cavity is between the isolation feature and the first gate stack and the second recess cavity is between the first gate stack and the second gate stack. A topmost surface of the first epi material has a first crystal plane and a topmost surface of the second epi material has a second crystal plane. The topmost surface of the etched first epi material has a third crystal plane different from both the first crystal plane and the second crystal plane.
摘要翻译: 一种制造半导体器件的方法。 该方法包括在衬底中形成隔离特征,在衬底上形成第一栅极堆叠和第二栅极堆叠,在衬底中形成第一凹陷腔和第二凹槽,在第一衬底中生长第一外延(epi)材料 凹槽和第二外延材料,并蚀刻第一外延材料和第二外延材料。 第一凹陷腔位于隔离特征和第一栅极堆叠之间,第二凹槽在第一栅极堆叠和第二栅极堆叠之间。 第一外延材料的最表面具有第一晶体面,第二外延材料的最上表面具有第二晶体面。 蚀刻的第一外延材料的最表面具有不同于第一晶面和第二晶面的第三晶面。
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公开(公告)号:US20130244389A1
公开(公告)日:2013-09-19
申请号:US13889846
申请日:2013-05-08
发明人: Yu-Hung CHENG , Chii-Horng LI , Tze-Liang LEE
IPC分类号: H01L29/66
CPC分类号: H01L29/66636 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/78 , H01L29/7848
摘要: A method for fabricating a semiconductor device, the method includes forming a gate stack over a major surface of a substrate. The method further includes recessing the substrate to form source and drain recess cavities adjacent to the gate stack in the substrate. The method further includes selectively growing a strained material in the source and drain recess cavities in the substrate using an LPCVD process, wherein the LPCVD process is performed at a temperature of about 660 to 700° C. and under a pressure of about 13 to 50 Torr, using SiH2Cl2, HCl, GeH4, B2H6, and H2 as reaction gases.
摘要翻译: 一种制造半导体器件的方法,所述方法包括在衬底的主表面上形成栅叠层。 该方法还包括使衬底凹陷以形成与衬底中的栅极堆叠相邻的源极和漏极凹腔。 该方法还包括使用LPCVD工艺选择性地生长衬底中的源极和漏极凹腔中的应变材料,其中LPCVD工艺在约660-700℃的温度和约13至50℃的压力下进行 Torr,使用SiH2Cl2,HCl,GeH4,B2H6和H2作为反应气体。
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