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公开(公告)号：US20230402321A1
公开(公告)日：2023-12-14
申请号：US18447539
申请日：2023-08-10
发明人： Po-Hsien CHENG , Chi-Ming YANG , Tze-Liang LEE
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76846 , H01L23/53238 , H01L23/53209 , H01L21/76844 , H01L21/7685 , H01L23/53266 , H01L23/5226
摘要： A layer of carbon (e.g., graphite or graphene) at a metal interface (e.g., between an MEOL interconnect and a gate contact or a source or drain region contact, between an MEOL contact plug and a BEOL metallization layer, and/or between BEOL conductive structures) is used to reduce contact resistance at the metal interface, which increases electrical performance of an electronic device. Additionally, in some implementations, the layer of carbon may help prevent heat transfer from a second metal to a first metal when the second metal is deposited over the first metal. This results in more symmetric deposition of the second metal, which reduces surface roughness and contact resistance at the metal interface. As an alternative, in some implementations, the layer of carbon is etched before deposition of the second metal in order to reduce contact resistance at the metal interface.
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公开(公告)号：US20220359515A1
公开(公告)日：2022-11-10
申请号：US17313451
申请日：2021-05-06
发明人： Pei-Yu CHOU , Yi-Ting FU , Ting-Gang CHEN , Tze-Liang LEE
IPC分类号： H01L27/092 , H01L29/06 , H01L29/66 , H01L29/78
摘要： A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.
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公开(公告)号：US20220319862A1
公开(公告)日：2022-10-06
申请号：US17391660
申请日：2021-08-02
发明人： Ching-Yu CHANG , Jei-Ming CHEN , Tze-Liang LEE
IPC分类号： H01L21/311 , H01L21/033
摘要： A method includes forming a dielectric layer over a substrate; forming a patterned amorphous silicon layer over a dielectric layer; depositing a first spacer layer over the patterned amorphous silicon layer; depositing a second spacer layer over the first spacer layer; forming a photoresist having an opening over the substrate; depositing a hard mask layer in the opening of the photoresist; after depositing the hard mask layer in the opening of the photoresist, removing the photoresist; and performing an etching process to etch the dielectric layer by using the patterned amorphous silicon layer, the first spacer layer, the second spacer layer, and the hard mask layer as an etch mask, in which the etching process etches the second spacer layer at a slower etch rate than etching the first spacer layer.
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公开(公告)号：US20220208603A1
公开(公告)日：2022-06-30
申请号：US17696393
申请日：2022-03-16
发明人： Po-Cheng SHIH , Tze-Liang LEE , Jen-Hung WANG , Yu-Kai LIN , Su-Jen SUNG
IPC分类号： H01L21/768 , H01L23/532
摘要： A method for forming a semiconductor device structure is provided. The method includes successively forming a first multi-layer etch stop structure and an insulating layer over a first conductive feature. The insulating layer and the first multi-layer etch stop structure are successively etched to form an opening substantially aligned to the first conductive feature. A second conductive feature is formed in the opening. The formation of the first multi-layer etch stop structure and the second multi-layer etch stop structure includes forming a first metal-containing dielectric layer, forming a silicon-containing dielectric layer over the first metal-containing dielectric layer, and forming a second metal-containing dielectric layer over the silicon-containing dielectric layer. The second metal-containing dielectric layer has a material that is different from the material of the first metal-containing dielectric layer.
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公开(公告)号：US20220181143A1
公开(公告)日：2022-06-09
申请号：US17592091
申请日：2022-02-03
发明人： Tsai-Fu HSIAO , Kuang-Yuan HSU , Pei-Ren JENG , Tze-Liang LEE
IPC分类号： H01L21/02 , C23C16/455 , H01L21/687 , H01L21/677 , H01L21/67 , C23C16/54
摘要： An apparatus includes a vacuum chamber, a wafer transfer mechanism, a first gas source, a second gas source and a reuse gas pipe. The vacuum chamber is divided into at least three reaction regions including a first reaction region, a second reaction region and a third reaction region. The wafer transfer mechanism is structured to transfer a wafer from the first reaction region to the third reaction region via the second reaction region. The first gas source supplies a first gas to the first reaction region via a first gas pipe, and a second gas source supplies a second gas to the second reaction region via a second gas pipe. The reuse gas pipe is connected between the first reaction region and the third reaction region for supplying an unused first gas collected in the first reaction region to the third reaction region.
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公开(公告)号：US20140367768A1
公开(公告)日：2014-12-18
申请号：US14475107
申请日：2014-09-02
发明人： Yen-Ru LEE , Ming-Hua YU , Tze-Liang LEE , Chii-Horng LI , Pang-Yen TSAI , Lilly SU , Yi-Hung LIN , Yu-Hung CHENG
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02661 , H01L21/30604 , H01L21/30608 , H01L21/3065 , H01L21/3083 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/66545 , H01L29/66636 , H01L29/7845 , H01L29/7846
摘要： A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution.
摘要翻译： 一种用于制造半导体器件的方法包括在衬底中形成隔离特征，在衬底上形成栅叠层，在衬底中形成源/漏（S / D）凹槽，其中S / D凹腔位于 门堆叠和隔离功能。 该方法还包括在S / D凹陷空腔中形成外延（epi）材料，其中外延材料具有包括第一晶体面的上表面。 另外，该方法包括使用含氯气体对S / D凹腔中的外延材料进行再分配处理，其中第一晶面在再分布之后被转换为第二晶体面。
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公开(公告)号：US20230375920A1
公开(公告)日：2023-11-23
申请号：US18230062
申请日：2023-08-03
发明人： Ming-Hui WENG , Chen-Yu LIU , Chih-Cheng LIU , Yi-Chen KUO , Jia-Lin WEI , Yen-Yu CHEN , Jr-Hung LI , Yahru CHENG , Chi-Ming YANG , Tze-Liang LEE , Ching-Yu CHANG
IPC分类号： G03F7/004 , H01L21/033 , G03F7/00
CPC分类号： G03F7/004 , H01L21/0332 , G03F7/0035
摘要： A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
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公开(公告)号：US20230068625A1
公开(公告)日：2023-03-02
申请号：US17461166
申请日：2021-08-30
发明人： Wei-Ren WANG , Tze-Liang LEE , Jen-Hung WANG
IPC分类号： H01L23/522 , H01L21/768 , H01L21/311
摘要： A semiconductor structure includes a first dielectric layer, a first conductive feature, a second conductive feature, a first etch stop layer, and a conductive via. The first conductive feature and the second conductive feature are embedded in the first dielectric layer. The first etch stop layer is disposed over the dielectric layer. The conductive via is surrounded by the first etch stop layer and electrically connected to the first conductive feature, in which the conductive via is in contact with a top surface of the first etch stop layer.
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公开(公告)号：US20220336583A1
公开(公告)日：2022-10-20
申请号：US17479454
申请日：2021-09-20
发明人： Guan-Yao TU , Su-Jen SUNG , Tze-Liang LEE , Hong-Wei CHAN
IPC分类号： H01L29/06 , H01L29/423 , H01L29/786 , H01L23/528 , H01L21/477 , H01L29/66
摘要： A method includes forming a transistor over a front side of a substrate; forming a front-side interconnect structure over the transistor, the front-side interconnect structure comprising layers of conductive lines, and conductive vias interconnecting the layers of conductive lines; forming a first bonding layer over the front-side interconnect structure; forming a second bonding layer over a carrier substrate; bonding the front-side interconnect structure to the carrier substrate by pressing the first bonding layer against the second bonding layer; and forming a backside interconnect structure over a backside of the substrate after bonding the front-side interconnect structure to the carrier substrate.
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10.发明申请公开(公告)号：US20220102200A1
公开(公告)日：2022-03-31
申请号：US17301071
申请日：2021-03-24
发明人： Szu-Ping TUNG , Chun-Kai CHEN , Tze-Liang LEE , Yi-Nien SU
IPC分类号： H01L21/768 , H01L21/027 , H01L21/02 , H01L21/033
摘要： In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition having a composition including at least 50 atomic percentage carbon; depositing a second layer including silicon; and depositing a photosensitive layer on the second layer. In some implementations, the first layer is deposited by ALD, CVD, or PVD processes.
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