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公开(公告)号：US20160322499A1
公开(公告)日：2016-11-03
申请号：US15209103
申请日：2016-07-13
发明人： Lilly SU , Pang-Yen TSAI , Tze-Liang LEE , Chii-Horng LI , Yen-Ru LEE , Ming-Hua YU
IPC分类号： H01L29/78 , H01L21/8238 , H01L29/66 , H01L29/06 , H01L29/08 , H01L21/8234 , H01L29/04
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/0617 , H01L29/045 , H01L29/0653 , H01L29/0843 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device includes a first gate stack and a second gate stack over a substrate, an isolation structure in the substrate, a first epitaxial (epi) material in the substrate between the first gate stack and the isolation structure, and a second epi material in the substrate between the first gate stack and the second gate stack. The first gate stack is between the isolation structure and the second gate stack. The first epi material includes a first upper surface having a first crystal plane. The second epi material includes a second upper surface having a second crystal plane and a third upper surface having a third crystal plane, and first crystal plane is different from both the second crystal plane and the third crystal plane.
摘要翻译： 半导体器件包括在衬底上的第一栅极堆叠和第二栅极堆叠，衬底中的隔离结构，在第一栅极堆叠和隔离结构之间的衬底中的第一外延（epi）材料，以及第二外延材料 第一栅极堆叠和第二栅极堆叠之间的衬底。 第一栅极堆叠在隔离结构和第二栅极堆叠之间。 第一外延材料包括具有第一晶体平面的第一上表面。 第二外延材料包括具有第二晶面的第二上表面和具有第三晶面的第三上表面，并且第一晶面与第二晶面和第三晶面均不同。
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公开(公告)号：US20150091103A1
公开(公告)日：2015-04-02
申请号：US14567329
申请日：2014-12-11
发明人： Lilly SU , Pang-Yen TSAI , Tze-Liang LEE , Chii-Horng LI , Yen-Ru LEE , Ming-Hua YU
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/0617 , H01L29/045 , H01L29/0653 , H01L29/0843 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device includes a gate stack, an isolation structure and a strained feature. The gate stack is over a substrate. The isolation structure is in the substrate. The strained feature is disposed between the gate stack and the isolation structure and disposed in the substrate. The strained feature includes an upper surface adjacent to the isolation structure having a first crystal plane and a sidewall surface adjacent to the gate stack having a second crystal plane. The first crystal plane is different from the second crystal plane.
摘要翻译： 半导体器件包括栅极堆叠，隔离结构和应变特征。 栅极堆叠在衬底上。 隔离结构在衬底中。 应变特征设置在栅极堆叠和隔离结构之间并且设置在衬底中。 应变特征包括与隔离结构相邻的上表面，其具有第一晶体面和邻近具有第二晶体平面的栅极叠层的侧壁表面。 第一个晶面与第二个晶面不同。
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公开(公告)号：US20140367768A1
公开(公告)日：2014-12-18
申请号：US14475107
申请日：2014-09-02
发明人： Yen-Ru LEE , Ming-Hua YU , Tze-Liang LEE , Chii-Horng LI , Pang-Yen TSAI , Lilly SU , Yi-Hung LIN , Yu-Hung CHENG
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02661 , H01L21/30604 , H01L21/30608 , H01L21/3065 , H01L21/3083 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/66545 , H01L29/66636 , H01L29/7845 , H01L29/7846
摘要： A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution.
摘要翻译： 一种用于制造半导体器件的方法包括在衬底中形成隔离特征，在衬底上形成栅叠层，在衬底中形成源/漏（S / D）凹槽，其中S / D凹腔位于 门堆叠和隔离功能。 该方法还包括在S / D凹陷空腔中形成外延（epi）材料，其中外延材料具有包括第一晶体面的上表面。 另外，该方法包括使用含氯气体对S / D凹腔中的外延材料进行再分配处理，其中第一晶面在再分布之后被转换为第二晶体面。
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公开(公告)号：US20210083115A1
公开(公告)日：2021-03-18
申请号：US17089229
申请日：2020-11-04
发明人： Lilly SU , Chii-Horng LI , Ming-Hua YU , Pang-Yen TSAI , Tze-Liang LEE , Yen-Ru LEE
IPC分类号： H01L29/78 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/08 , H01L29/04 , H01L27/06 , H01L29/06
摘要： A method of manufacturing a semiconductor device includes forming a first gate stack over a substrate. The method further includes etching the substrate to define a cavity. The method further includes growing a first epitaxial (epi) material in the cavity, wherein the first epi material includes a first upper surface having a first crystal plane. The method further includes growing a second epi material on the first epi material, wherein the second epi material includes a second upper surface having the first crystal plane. The method further includes treating the second epi material, wherein treating the second epi material comprises causing the second upper surface to transform to a second crystal plane different from the first crystal plane.
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公开(公告)号：US10854748B2
公开(公告)日：2020-12-01
申请号：US15837546
申请日：2017-12-11
发明人： Lilly SU , Pang-Yen Tsai , Tze-Liang Lee , Chii-Horng Li , Yen-Ru Lee , Ming-Hua Yu
IPC分类号： H01L29/78 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/08 , H01L29/04 , H01L27/06 , H01L29/06
摘要： A semiconductor device includes a first gate stack over a substrate. The semiconductor device further includes a first epitaxial (epi) material in the substrate on a first side of the first gate stack. The first epi material includes a first upper surface having a first crystal plane. The semiconductor device further includes a second epi material in the substrate on a second side of the first gate stack opposite the first side. The second epi material includes a second upper surface having a second crystal plane, and the first crystal plane is different from the second crystal plane.
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公开(公告)号：US20180108777A1
公开(公告)日：2018-04-19
申请号：US15837546
申请日：2017-12-11
发明人： Lilly SU , Pang-Yen TSAI , Tze-Liang LEE , Chii-Horng LI , Yen-Ru LEE , Ming-Hua YU
IPC分类号： H01L29/78 , H01L29/66 , H01L29/04 , H01L29/08 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L29/06
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/0617 , H01L29/045 , H01L29/0653 , H01L29/0843 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device includes a first gate stack over a substrate. The semiconductor device further includes a first epitaxial (epi) material in the substrate on a first side of the first gate stack. The first epi material includes a first upper surface having a first crystal plane. The semiconductor device further includes a second epi material in the substrate on a second side of the first gate stack opposite the first side. The second epi material includes a second upper surface having a second crystal plane, and the first crystal plane is different from the second crystal plane.
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公开(公告)号：US20160336448A1
公开(公告)日：2016-11-17
申请号：US15223597
申请日：2016-07-29
发明人： Yen-Ru LEE , Ming-Hua YU , Tze-Liang LEE , Chii-Horng LI , Pang-Yen TSAI , Lilly SU , Yi-Hung LIN , Yu-Hung CHENG
IPC分类号： H01L29/78 , H01L21/3065 , H01L21/308 , H01L21/8234 , H01L29/08 , H01L21/02 , H01L29/66 , H01L21/8238 , H01L29/04 , H01L21/306
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02661 , H01L21/30604 , H01L21/30608 , H01L21/3065 , H01L21/3083 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/66545 , H01L29/66636 , H01L29/7845 , H01L29/7846
摘要： A method of fabricating a semiconductor device. The method includes forming an isolation feature in a substrate, forming a first gate stack and a second gate stack over the substrate, forming a first recess cavity and a second recess cavity in the substrate, growing a first epitaxial (epi) material in the first recess cavity and a second epi material in the second recess cavity, and etching the first epi material and the second epi material. The first recess cavity is between the isolation feature and the first gate stack and the second recess cavity is between the first gate stack and the second gate stack. A topmost surface of the first epi material has a first crystal plane and a topmost surface of the second epi material has a second crystal plane. The topmost surface of the etched first epi material has a third crystal plane different from both the first crystal plane and the second crystal plane.
摘要翻译： 一种制造半导体器件的方法。 该方法包括在衬底中形成隔离特征，在衬底上形成第一栅极堆叠和第二栅极堆叠，在衬底中形成第一凹陷腔和第二凹槽，在第一衬底中生长第一外延（epi）材料 凹槽和第二外延材料，并蚀刻第一外延材料和第二外延材料。 第一凹陷腔位于隔离特征和第一栅极堆叠之间，第二凹槽在第一栅极堆叠和第二栅极堆叠之间。 第一外延材料的最表面具有第一晶体面，第二外延材料的最上表面具有第二晶体面。 蚀刻的第一外延材料的最表面具有不同于第一晶面和第二晶面的第三晶面。
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