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公开(公告)号：US11843038B2
公开(公告)日：2023-12-12
申请号：US17589180
申请日：2022-01-31
发明人： Ming-Shuan Li , Zi-Ang Su , Ying-Keung Leung
IPC分类号： H01L29/417 , H01L29/78 , H01L29/66 , H01L29/73 , H01L29/423
CPC分类号： H01L29/41708 , H01L29/42304 , H01L29/6681 , H01L29/66234 , H01L29/73 , H01L29/785
摘要： Embodiments include a first set of fins having an emitter of a bipolar junction transistor (BJT) disposed over the first set of fins, a second set of fins having a base of the BJT disposed over the second set of fins, and a third set of fins having a collector of the BJT disposed over the third set of fins. A first gate structure is disposed over the first set of fins adjacent to the emitter. A second gate structure is disposed over the second set of fins adjacent to the base. A third gate structure is disposed over the third set of fins adjacent to the collector. The first gate structure, second gate structure, and third gate structure are physically and electrically separated.
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公开(公告)号：US11437479B2
公开(公告)日：2022-09-06
申请号：US16883227
申请日：2020-05-26
发明人： Kuo-Cheng Chiang , Chi-Wen Liu , Ying-Keung Leung
IPC分类号： H01L29/417 , H01L29/66 , H01L21/8234 , H01L21/84 , H01L27/092 , H01L29/78 , H01L21/8238 , H01L27/108 , H01L27/12 , H01L27/088 , H01L29/06 , H01L29/45
摘要： A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
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公开(公告)号：US10818658B2
公开(公告)日：2020-10-27
申请号：US16045266
申请日：2018-07-25
发明人： Kuo-Cheng Ching , Ying-Keung Leung , Chi On Chui
IPC分类号： H01L21/02 , H01L21/8234 , H01L27/088 , H01L29/66 , H01L29/06 , H01L29/423 , H01L27/092 , H01L21/8238 , H01L21/32 , H01L21/3105
摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.
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公开(公告)号：US20180350803A1
公开(公告)日：2018-12-06
申请号：US16045266
申请日：2018-07-25
发明人： Kuo-Cheng Ching , Ying-Keung Leung , Chi On Chui
IPC分类号： H01L27/088 , H01L21/02 , H01L21/8234 , H01L29/66 , H01L29/06 , H01L29/423
摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.
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公开(公告)号：US10096693B2
公开(公告)日：2018-10-09
申请号：US15896394
申请日：2018-02-14
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L27/11 , H01L27/02
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes a bottom spacer formed on a lower part of a sidewall of the gate structure and an upper spacer formed on an upper part of the sidewall of the gate structure. In addition, the upper spacer includes an air gap formed in a dielectric material.
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公开(公告)号：US10008603B2
公开(公告)日：2018-06-26
申请号：US15355844
申请日：2016-11-18
发明人： Huan-Sheng Wei , Hung-Li Chiang , Chia-Wen Liu , Yi-Ming Sheu , Zhiqiang Wu , Chung-Cheng Wu , Ying-Keung Leung
IPC分类号： H01L29/78 , H01L29/66 , H01L29/08 , H01L29/165 , H01L21/02 , H01L21/311 , H01L21/306 , H01L29/06 , H01L29/423
CPC分类号： H01L29/7851 , H01L21/02236 , H01L21/02532 , H01L21/30604 , H01L21/31111 , H01L29/0673 , H01L29/0847 , H01L29/165 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/78654 , H01L29/78696
摘要： A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.
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公开(公告)号：US20180151688A1
公开(公告)日：2018-05-31
申请号：US15409617
申请日：2017-01-19
发明人： Kuo-Cheng Ching , Shi-Ning Ju , Chih-Hao Wang , Ying-Keung Leung
IPC分类号： H01L29/66 , H01L21/02 , H01L29/51 , H01L21/311
CPC分类号： H01L21/31116 , H01L21/823821 , H01L27/0924 , H01L29/6653 , H01L29/66795 , H01L29/7851
摘要： A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.
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公开(公告)号：US09941279B2
公开(公告)日：2018-04-10
申请号：US15226007
申请日：2016-08-02
IPC分类号： H01L21/308 , H01L21/8234 , H01L29/78 , H01L27/088 , H01L29/06 , H01L21/762 , H01L27/108 , H01L21/3065
CPC分类号： H01L27/0886 , H01L21/3065 , H01L21/3085 , H01L21/3086 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L27/088 , H01L27/108 , H01L29/0649 , H01L29/0653 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure includes a substrate, at least one active fin present on the substrate, and at least one isolation dielectric surrounding the active fin. The isolation dielectric has at least one trench therein. The semiconductor structure further includes at least one dielectric liner present on at least one sidewall of the trench of the isolation dielectric, and at least one filling dielectric present in the trench of the isolation dielectric.
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公开(公告)号：US09911824B2
公开(公告)日：2018-03-06
申请号：US14858862
申请日：2015-09-18
IPC分类号： H01L27/088 , H01L29/66 , H01L29/78 , H01L27/11 , H01L27/02
CPC分类号： H01L29/6656 , H01L21/7682 , H01L21/76897 , H01L27/0207 , H01L27/0248 , H01L27/1104 , H01L29/66545 , H01L29/66795 , H01L29/6681 , H01L29/785
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes a bottom spacer formed on a lower part of a sidewall of the gate structure and an upper spacer formed on an upper part of the sidewall of the gate structure. In addition, the upper spacer includes an air gap formed in a dielectric material.
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公开(公告)号：US09716096B1
公开(公告)日：2017-07-25
申请号：US15194711
申请日：2016-06-28
IPC分类号： H01L27/088 , H01L27/11 , H01L21/8234 , H01L29/06 , H01L29/66 , H01L21/3115 , H01L21/02
CPC分类号： H01L27/1104 , H01L21/02126 , H01L21/31155 , H01L21/823431 , H01L27/1116 , H01L29/0653 , H01L29/66795
摘要： A semiconductor structure includes a first fin structure, a gate structure, a first spacer, and a second space spacer. The gate structure traverses the first fin structure. The first fin structure has an exposed portion exposed out of the gate structure. The first spacer is positioned at and in contact with a side of the exposed portion of the first fin structure. The second space spacer is positioned at and in contact with another side of the exposed portion of the first fin structure. The first spacer has a top surface over than a top surface of the second spacer.
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