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    Lateral PNP Bipolar Transistor with Narrow Trench Emitter
    1.
    发明申请
    Lateral PNP Bipolar Transistor with Narrow Trench Emitter 有权
    具有窄沟槽发射极的横向PNP双极晶体管

    公开(公告)号：US20130075746A1

    公开(公告)日：2013-03-28

    申请号：US13242970

    申请日：2011-09-23

    申请人： Shekar Mallikarjunaswamy ,  François Hébert

    发明人： Shekar Mallikarjunaswamy ,  François Hébert

    IPC分类号： H01L29/04 ,  H01L21/331

    CPC分类号： H01L29/6625 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2254 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/735

    摘要： A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.

    摘要翻译： 横向双极晶体管包括沟槽发射极和沟槽集电极区域，以形成超窄的发射极区域，从而提高发射极效率。 使用相同的沟槽工艺来形成发射极/集电极沟槽以及沟槽隔离结构，使得不需要额外的处理步骤来形成沟槽发射极和集电极。 在本发明的实施例中，可以使用离子注入形成在半导体层中的沟槽中形成沟槽发射极和沟槽集电极区域。 在其他实施例中，沟槽发射极和沟槽集电极区域可以通过从重掺杂的多晶硅填充的沟槽中的掺杂剂的扩散而形成。

    Lateral PNP bipolar transistor with narrow trench emitter
    2.
    发明授权
    Lateral PNP bipolar transistor with narrow trench emitter 有权
    具有窄沟槽发射极的横向PNP双极晶体管

    公开(公告)号：US09312335B2

    公开(公告)日：2016-04-12

    申请号：US13242970

    申请日：2011-09-23

    申请人： Shekar Mallikarjunaswamy ,  François Hébert

    发明人： Shekar Mallikarjunaswamy ,  François Hébert

    IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/735 ,  H01L29/66

    CPC分类号： H01L29/6625 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2254 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/735

    摘要： A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.

    摘要翻译： 横向双极晶体管包括沟槽发射极和沟槽集电极区域，以形成超窄的发射极区域，从而提高发射极效率。 使用相同的沟槽工艺来形成发射极/集电极沟槽以及沟槽隔离结构，使得不需要额外的处理步骤来形成沟槽发射极和集电极。 在本发明的实施例中，可以使用离子注入形成在半导体层中的沟槽中形成沟槽发射极和沟槽集电极区域。 在其他实施例中，沟槽发射极和沟槽集电极区域可以通过从重掺杂的多晶硅填充的沟槽中的掺杂剂的扩散而形成。

    Lateral PNP Bipolar Transistor Formed with Multiple Epitaxial Layers
    3.
    发明申请
    Lateral PNP Bipolar Transistor Formed with Multiple Epitaxial Layers 有权
    形成多个外延层的横向PNP双极晶体管

    公开(公告)号：US20130075741A1

    公开(公告)日：2013-03-28

    申请号：US13243002

    申请日：2011-09-23

    申请人： Shekar Mallikarjunaswamy ,  François Hébert

    发明人： Shekar Mallikarjunaswamy ,  François Hébert

    IPC分类号： H01L29/04 ,  H01L21/331 ,  H01L29/735

    CPC分类号： H01L29/735 ,  H01L21/26586 ,  H01L21/761 ,  H01L29/0646 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/41766 ,  H01L29/42304 ,  H01L29/6625 ,  H01L29/66659 ,  H01L29/7393 ,  H01L29/7835

    摘要： A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance.

    摘要翻译： 具有深发射极和深集电极区域的横向双极晶体管使用相同导电类型的多个外延层来形成。 在不使用沟槽的情况下形成深发射极和深集电极区域。 在每个外延层中形成垂直排列的扩散区，使得扩散区在退火之后被合并成连续的扩散区，起到发射极或集电极或隔离结构的作用。 在另一个实施例中，使用沟槽发射极和沟槽集电极区域形成横向沟槽PNP双极晶体管。 在另一个实施例中，形成具有合并的LDMOS晶体管的横向PNP双极晶体管，以实现高性能。

    Charged balanced devices with shielded gate trench
    6.
    发明授权
    Charged balanced devices with shielded gate trench 有权
    带屏蔽栅极沟槽的均衡器件

    公开(公告)号：US09356134B2

    公开(公告)日：2016-05-31

    申请号：US14312687

    申请日：2014-06-24

    申请人： François Hébert

    发明人： François Hébert

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

    CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734

    摘要： This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.

    摘要翻译： 本发明公开了一种设置在半导体衬底上的半导体功率器件，包括具有填充所述深沟槽的外延层的多个深沟槽和覆盖半导体衬底上的所述深沟槽的顶表面之上的区域的同时生长的顶部外延层。 设置在所述顶部外延层中的多个沟槽MOSFET单元，顶部外延层用作主体区域，并且半导体衬底用作漏极区域，由此通过深沟槽中的外延层之间的电荷平衡和 半导体衬底中的与深沟槽横向相邻的区域。 每个沟槽MOSFET单元还包括沟槽栅极和栅极屏蔽掺杂剂区域，其设置在用于每个沟槽MOSFET单元的每个沟槽栅极的下方并基本对齐，用于在电压击穿期间屏蔽沟槽栅极。

    Source and body contact structure for trench-DMOS devices using polysilicon
    7.
    发明授权
    Source and body contact structure for trench-DMOS devices using polysilicon 有权
    使用多晶硅的沟槽DMOS器件的源和体接触结构

    公开(公告)号：US08703563B2

    公开(公告)日：2014-04-22

    申请号：US13559490

    申请日：2012-07-26

    申请人： François Hébert ,  Anup Bhalla

    发明人： François Hébert ,  Anup Bhalla

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

    摘要： A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译： 半导体器件包括栅极电极，设置在栅电极旁边的顶部源极区域，设置在栅极电极底部的漏极区域，设置在源极区域和栅极电极顶部的氧化物以及掺杂多晶硅间隔物 沿着源区域的侧壁和氧化物的侧壁设置。 还公开了制造这种装置的方法。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

    SUPER-SELF-ALIGNED TRENCH-DMOS STRUCTURE AND METHOD
    8.
    发明申请
    SUPER-SELF-ALIGNED TRENCH-DMOS STRUCTURE AND METHOD 有权
    超自对准TRENCH-DMOS结构和方法

    公开(公告)号：US20140004671A1

    公开(公告)日：2014-01-02

    申请号：US13709614

    申请日：2012-12-10

    申请人： François Hébert

    发明人： François Hébert

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66734 ,  H01L21/2257 ,  H01L29/04 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/7813

    摘要： A body layer is formed in an epitaxial layer and a gate electrode formed in a trench in the body and epitaxial layer. A gate insulator is disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the epitaxial layer. A cap insulator is disposed on top of the gate electrode. A doped spacer is disposed along a sidewall of the source and a sidewall of the gate insulator. The body layer next to the polysilicon spacer is etched back below the bottom of the polysilicon spacer. Dopants are diffused from the spacer to form the source region.

    摘要翻译： 主体层形成在外延层中，形成在主体和外延层中的沟槽中的栅电极。 栅极绝缘体沿着栅极电极的侧壁设置在栅电极和源极之间，在栅电极和P体之间以及栅电极和外延层之间。 盖绝缘体设置在栅电极的顶部。 掺杂间隔物沿着源极的侧壁和栅极绝缘体的侧壁设置。 多晶硅间隔物旁边的主体层被蚀刻回多晶硅间隔物的底部之下。 掺杂剂从间隔物扩散以形成源区。

    SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON
    10.
    发明申请
    SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON 有权
    使用POLYSILICON的TRENCH-DMOS器件的源和体接触结构

    公开(公告)号：US20120286356A1

    公开(公告)日：2012-11-15

    申请号：US13559490

    申请日：2012-07-26

    申请人： François Hébert ,  Anup Bhalla

    发明人： François Hébert ,  Anup Bhalla

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

    摘要： A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译： 半导体器件包括栅极电极，设置在栅电极旁边的顶部源极区域，设置在栅极电极底部的漏极区域，设置在源极区域和栅极电极顶部的氧化物以及掺杂多晶硅间隔物 沿着源区域的侧壁和氧化物的侧壁设置。 还公开了制造这种装置的方法。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。