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    Semiconductor package and method of fabricating the same
    2.
    发明授权
    Semiconductor package and method of fabricating the same 有权

    公开(公告)号：US11694969B2

    公开(公告)日：2023-07-04

    申请号：US17171708

    申请日：2021-02-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngwoo Park

    IPC: H01L23/552 ,  H01L25/18 ,  H01L21/56 ,  H01L23/538 ,  H01L23/528

    CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L23/5286 ,  H01L23/5386 ,  H01L25/18

    Abstract: A semiconductor package is disclosed. The semiconductor package may include a substrate, a first semiconductor chip on the substrate, an inner mold layer provided on the substrate to at least partially enclose the first semiconductor chip, an inner shielding layer provided on the substrate to at least partially enclose the inner mold layer, a second semiconductor chip stack on the inner shielding layer, an outer mold layer provided on the substrate to at least partially enclose the inner shielding layer and the second semiconductor chip stack, and an outer shielding layer at least partially enclosing the outer mold layer. Each of the inner and outer shielding layers may include a conductive material, and the inner shielding layer may be electrically connected to a ground pad of the substrate.

    SEMICONDUCTOR DEVICE HAVING INTERCONNECTION STRUCTURE
    4.
    发明申请
    SEMICONDUCTOR DEVICE HAVING INTERCONNECTION STRUCTURE 审中-公开

    公开(公告)号：US20190363012A1

    公开(公告)日：2019-11-28

    申请号：US16534195

    申请日：2019-08-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

    IPC: H01L21/768 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L23/532 ,  H01L23/522

    Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

    3-Dimensional semiconductor memory device and operating method thereof
    6.
    发明授权
    3-Dimensional semiconductor memory device and operating method thereof 有权
    3维半导体存储器件及其操作方法

    公开(公告)号：US09595346B2

    公开(公告)日：2017-03-14

    申请号：US15157720

    申请日：2016-05-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changhyun Lee ,  Dohyun Lee ,  Youngwoo Park ,  Su Jin Ahn ,  Jaeduk Lee

    IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  H01L27/115 ,  H01L23/528 ,  H01L29/04 ,  H01L29/16

    CPC classification number: H01L27/11524 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16

    Abstract: Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns. The three-dimensional semiconductor memory device further comprising a first ground selection transistor that includes a first gate pattern, adjacent to the first substrate and the first pillar, and a second ground selection transistor that includes a second gate pattern positioned on the first gate pattern and the first pillar, and wherein the first ground selection transistor is not programmable, and the second ground selection transistor is programmable.

    Abstract translation: 公开了一种三维半导体存储器件，包括形成在第一衬底上的单元阵列和形成在第二衬底上的外围电路，所述外围电路至少部分地与第一衬底重叠，其中外围电路被配置为提供控制信号 单元格阵列。 电池阵列包括在第一衬底上交替堆叠的绝缘图案和栅极图案，以及至少第一柱，其沿垂直于第一衬底的方向形成，并且通过绝缘图案和栅极图案与第一衬底接触。 所述三维半导体存储器件还包括第一接地选择晶体管，其包括与所述第一衬底和所述第一柱相邻的第一栅极图案，以及第二接地选择晶体管，所述第二接地选择晶体管包括位于所述第一栅极图案上的第二栅极图案， 第一支柱，并且其中第一接地选择晶体管不可编程，并且第二接地选择晶体管是可编程的。

    THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    8.
    发明申请
    THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    三维半导体存储器件及其制造方法

    公开(公告)号：US20150303215A1

    公开(公告)日：2015-10-22

    申请号：US14753713

    申请日：2015-06-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SUNG-IL CHANG ,  Youngwoo Park ,  Jaegoo Lee

    IPC: H01L27/115 ,  H01L29/423

    CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/42324 ,  H01L29/4234

    Abstract: A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.

    Abstract translation: 一种3D半导体器件包括：电极结构，其具有堆叠在基板上的电极，穿透电极结构的半导体图案，插入在半导体图案和电极结构之间的电荷存储图案，以及插入在电荷存储图案和电极结构之间的绝缘图案。 每个隔离绝缘图案包围半导体图案，并且电荷存储图案彼此水平间隔并且以这样的方式配置，以使得每个隔离绝缘图案围绕相应的一个半导体图案设置。 而且，每个电荷存储图案包括多个水平段，每个水平段插入垂直相邻的电极之间。

    Vertical resistance memory device and a read method thereof
    9.
    发明授权
    Vertical resistance memory device and a read method thereof 有权
    垂直电阻存储器件及其读取方法

    公开(公告)号：US09036398B2

    公开(公告)日：2015-05-19

    申请号：US13708018

    申请日：2012-12-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jintaek Park ,  Youngwoo Park ,  Jungdal Choi

    IPC: G11C11/00 ,  G11C11/21 ,  G11C13/00

    CPC classification number: G11C11/21 ,  G11C8/12 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/004 ,  G11C16/0408 ,  G11C16/08 ,  G11C2213/71 ,  G11C2213/78

    Abstract: A read method of a vertical resistance memory device including resistance memory cells arranged in a three-dimensional array includes selecting a block from a plurality of blocks, applying a read voltage to a word line selected from word lines of the block, applying a sensing reference voltage to bit lines sharing the plurality of blocks, applying a string selection voltage to a string selection transistor through a string selection line selected from a plurality of string selection lines of the block, wherein the string selection line is connected to a gate of the string selection transistor; and determining a memory state of a memory cell selected from the plurality of resistance memory cells by the word line and the string selection line based on a current flowing through the memory cell, wherein the word line is connected through a corresponding horizontal electrode to the memory cell.

    Abstract translation: 包括以三维阵列布置的电阻存储单元的垂直电阻存储器件的读取方法包括从多个块中选择一个块，向从块的字线选择的字线施加读取电压，施加感测参考 共享多个块的电压对位线，通过从块的多个串选择线中选择的串选择线将字符串选择电压施加到字符串选择晶体管，其中字符串选择线连接到字符串的门 选择晶体管; 并且基于流过所述存储单元的电流，通过所述字线和所述串选择线来确定从所述多个电阻存储单元中选择的存储单元的存储状态，其中所述字线通过相应的水平电极连接到所述存储器 细胞。

    Three-dimensional semiconductor memory devices
    10.
    发明授权
    Three-dimensional semiconductor memory devices 有权
    三维半导体存储器件

    公开(公告)号：US08796091B2

    公开(公告)日：2014-08-05

    申请号：US14012588

    申请日：2013-08-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Il Chang ,  Youngwoo Park ,  Kwang Soo Seol

    IPC: H01L21/336

    CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    Abstract: Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.

    Abstract translation: 提供三维半导体器件。 一种器件包括：电极结构，包括依次层叠在衬底上的导电图案，穿透电极结构的半导体图案，以及包括与导电图案相邻的沟道区域和沟道区域之间的垂直相邻区域;以及从外侧壁延伸的半导体连接层 的半导体图案以将半导体图案连接到基板。

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