公开(公告)号：US11335680B2

公开(公告)日：2022-05-17

申请号：US16912427

申请日：2020-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol Song ,  Seungha Oh ,  Rakhwan Kim ,  Minjung Park ,  Dongsoo Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/66

Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.

公开(公告)号：US20220367320A1

公开(公告)日：2022-11-17

申请号：US17560495

申请日：2021-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojin Lee ,  Kwangjin Moon ,  Seungha Oh

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00

Abstract: An integrated circuit device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first insulating layer on the first surface of the semiconductor substrate, an electrode landing pad positioned on the first surface of the semiconductor substrate and having a sidewall surrounded by the first insulating layer, a top surface apart from the first surface of the semiconductor substrate, and a bottom surface opposite to the top surface, and a through-electrode configured to penetrate through the semiconductor substrate and contact the top surface of the electrode landing pad, wherein a horizontal width of the top surface of the electrode landing pad is less than a horizontal width of the bottom surface of the electrode landing pad and greater than a horizontal width of a bottom surface of the through-electrode in contact with the top surface of the electrode landing pad.

公开(公告)号：US20210151432A1

公开(公告)日：2021-05-20

申请号：US16912427

申请日：2020-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol Song ,  Seungha Oh ,  Rakhwan Kim ,  Minjung Park ,  Dongsoo Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/51

Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.

公开(公告)号：US11990473B2

公开(公告)日：2024-05-21

申请号：US17723532

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol Song ,  Seungha Oh ,  Rakhwan Kim ,  Minjung Park ,  Dongsoo Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.

公开(公告)号：US11728347B2

公开(公告)日：2023-08-15

申请号：US17494275

申请日：2021-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Weonhong Kim ,  Pilkyu Kang ,  Yuichiro Sasaki ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun ,  Kughwan Kim ,  Seungha Oh

IPC: H01L27/12 ,  H01L21/762 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/76224 ,  H01L27/0203 ,  H01L27/02 ,  H01L29/78

Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

公开(公告)号：US12167596B2

公开(公告)日：2024-12-10

申请号：US18150523

申请日：2023-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungha Oh ,  Weonhong Kim ,  Hoonjoo Na

IPC: H10B43/20 ,  H10B12/00 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A three-dimensional semiconductor device includes a first substrate; a plurality of first transistors on the first substrate; a second substrate on the plurality of first transistors; a plurality of second transistors on the second substrate; and an interconnection portion electrically connecting the plurality of first transistors and the plurality of second transistors. Each of the plurality of first transistors includes a first gate insulating film on the first substrate and having a first hydrogen content. Each of the plurality of second transistors includes a second gate insulating film on the second substrate and having a second hydrogen content. The second hydrogen content is greater than the first hydrogen content.

公开(公告)号：US11901356B2

公开(公告)日：2024-02-13

申请号：US16817069

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungha Oh ,  Pil-Kyu Kang ,  Kughwan Kim ,  Weonhong Kim ,  Yuichiro Sasaki ,  Sang Woo Lee ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun

IPC: H01L27/06 ,  H01L23/48 ,  H10B41/60 ,  H10B43/20 ,  H10B63/00

CPC classification number: H01L27/0688 ,  H01L23/481 ,  H10B41/60 ,  H10B43/20 ,  H10B63/30 ,  H10B63/84

Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).

公开(公告)号：US11610838B2

公开(公告)日：2023-03-21

申请号：US17367773

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuichiro Sasaki ,  Sungkeun Lim ,  Pil-Kyu Kang ,  Weonhong Kim ,  Seungha Oh ,  Yongho Ha ,  Sangjin Hyun

IPC: H01L23/522 ,  H01L23/50 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

公开(公告)号：US11552096B2

公开(公告)日：2023-01-10

申请号：US17160874

申请日：2021-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungha Oh ,  Weonhong Kim ,  Hoonjoo Na

IPC: H01L27/11578 ,  H01L27/11524 ,  H01L27/088 ,  H01L27/11519 ,  H01L27/108 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11551

Abstract: A three-dimensional semiconductor device includes a first substrate; a plurality of first transistors on the first substrate; a second substrate on the plurality of first transistors; a plurality of second transistors on the second substrate; and an interconnection portion electrically connecting the plurality of first transistors and the plurality of second transistors. Each of the plurality of first transistors includes a first gate insulating film on the first substrate and having a first hydrogen content. Each of the plurality of second transistors includes a second gate insulating film on the second substrate and having a second hydrogen content. The second hydrogen content is greater than the first hydrogen content.

公开(公告)号：US20220254779A1

公开(公告)日：2022-08-11

申请号：US17723532

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol Song ,  Seungha Oh ,  Rakhwan Kim ,  Minjung Park ,  Dongsoo Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/66

Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.