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    Semiconductor devices having highly integrated sheet and wire patterns therein
    1.
    发明授权
    Semiconductor devices having highly integrated sheet and wire patterns therein 有权

    公开(公告)号：US12230630B2

    公开(公告)日：2025-02-18

    申请号：US17571954

    申请日：2022-01-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung In Choi ,  Do Young Choi ,  Dong Myoung Kim ,  Jin Bum Kim ,  Hae Jun Yu

    IPC: H01L27/088 ,  H01L21/8234

    Abstract: A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern. A second gate insulating film is wrapped around each of the plurality of wire patterns.

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12080796B2

    公开(公告)日：2024-09-03

    申请号：US17462026

    申请日：2021-08-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung In Choi ,  Hae Jun Yu ,  Sung Hun Jung

    IPC: H01L29/78 ,  H01L23/528 ,  H01L29/08

    CPC classification number: H01L29/7851 ,  H01L23/5283 ,  H01L29/0847

    Abstract: A semiconductor device includes; an active pattern on a substrate, gate structures in which each gate structure includes a gate electrode intersecting the active pattern and a gate capping pattern on the gate electrode, a source/drain pattern disposed on the active pattern between adjacent gate structures, a lower active contact connected to the source/drain pattern, an etching stop film extending along an upper surface of the lower active contact without contacting an upper surface of the gate capping pattern, and an upper active contact connected to the lower active contact, wherein a bottom surface of the upper active contact is lower than the upper surface of the gate capping pattern.

    SEMICONDUCTOR DEVICES HAVING HIGHLY INTEGRATED SHEET AND WIRE PATTERNS THEREIN
    3.
    发明申请
    SEMICONDUCTOR DEVICES HAVING HIGHLY INTEGRATED SHEET AND WIRE PATTERNS THEREIN 有权

    公开(公告)号：US20220399330A1

    公开(公告)日：2022-12-15

    申请号：US17571954

    申请日：2022-01-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung In Choi ,  Do Young Choi ,  Dong Myoung Kim ,  Jin Bum Kim ,  Hae Jun Yu

    IPC: H01L27/088 ,  H01L21/8234

    Abstract: A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern. A second gate insulating film is wrapped around each of the plurality of wire patterns.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240372002A1

    公开(公告)日：2024-11-07

    申请号：US18775240

    申请日：2024-07-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung In Choi ,  Hae Jun Yu ,  Sung Hun Jung

    IPC: H01L29/78 ,  H01L23/528 ,  H01L29/08

    Abstract: A semiconductor device includes; an active pattern on a substrate, gate structures in which each gate structure includes a gate electrode intersecting the active pattern and a gate capping pattern on the gate electrode, a source/drain pattern disposed on the active pattern between adjacent gate structures, a lower active contact connected to the source/drain pattern, an etching stop film extending along an upper surface of the lower active contact without contacting an upper surface of the gate capping pattern, and an upper active contact connected to the lower active contact, wherein a bottom surface of the upper active contact is lower than the upper surface of the gate capping pattern.

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    7.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20160359008A1

    公开(公告)日：2016-12-08

    申请号：US15174412

    申请日：2016-06-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung In Choi ,  Bon Young Koo ,  Hyun Gi Hong

    IPC: H01L29/417 ,  H01L21/3115 ,  H01L21/311 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08

    CPC classification number: H01L29/41791 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

    Abstract: A method of manufacturing a semiconductor device includes forming active fins on a substrate; forming source/drain regions on the active fins on both sides of a gate structure, the gate structure extending in a direction intersecting with a direction in which the active fins extend; forming an etch stop layer on the source/drain regions; forming an interlayer dielectric layer on the etch stop layer; forming a first opening by partially removing the interlayer dielectric layer so as not to expose the etch stop layer; forming an impurity region within the interlayer dielectric layer by implanting a first impurity ion through the first opening; forming a second opening by removing the impurity region so as to expose the etch stop layer; implanting a second impurity ion into the exposed etch stop layer; and removing the exposed etch stop layer.

    Abstract translation: 半导体器件的制造方法包括：在基板上形成有源翅片; 在栅极结构两侧的活性鳍片上形成源极/漏极区域，栅极结构在与活性鳍片延伸的方向相交的方向上延伸; 在源/漏区上形成蚀刻停止层; 在所述蚀刻停止层上形成层间介质层; 通过部分去除所述层间电介质层以形成不暴露所述蚀刻停止层而形成第一开口; 通过在第一开口中注入第一杂质离子，在层间电介质层内形成杂质区; 通过去除杂质区域形成第二开口以暴露蚀刻停止层; 将第二杂质离子注入到暴露的蚀刻停止层中; 并去除暴露的蚀刻停止层。

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