公开(公告)号：US12133393B2

公开(公告)日：2024-10-29

申请号：US17502380

申请日：2021-10-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Do Young Choi ,  Kab Jin Nam ,  In Bong Pok ,  Dae Won Ha ,  Musarrat Hasan

IPC: H01L27/11592 ,  H01L21/02 ,  H01L21/28 ,  H01L27/1159 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B51/30 ,  H10B51/40

CPC classification number: H10B51/40 ,  H01L21/0259 ,  H01L29/0665 ,  H01L29/40111 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78696 ,  H10B51/30

Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate including a first region and a second region such that the second region is separated from the first region; forming a metal oxide film on the first region of the substrate and the second region of the substrate; forming an upper metal material film on the metal oxide film on the first region of the substrate such that the upper metal material film does not overlap the metal oxide film on the second region of the substrate; and simultaneously annealing the upper metal material film and the metal oxide film to form a ferroelectric insulating film on the first region of the substrate and form a paraelectric insulating film on the second region of the substrate.

公开(公告)号：US12230630B2

公开(公告)日：2025-02-18

申请号：US17571954

申请日：2022-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung In Choi ,  Do Young Choi ,  Dong Myoung Kim ,  Jin Bum Kim ,  Hae Jun Yu

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern. A second gate insulating film is wrapped around each of the plurality of wire patterns.

公开(公告)号：US20220415931A1

公开(公告)日：2022-12-29

申请号：US17693883

申请日：2022-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Il Park ,  Jae Hyun Park ,  Do Young Choi ,  Yoshinao Harada ,  Dae Won Ha

IPC: H01L27/12 ,  H01L21/822

Abstract: A semiconductor device comprises a substrate, a first active pattern on the substrate and extending in a first direction, a second active pattern extending in the first direction spaced apart from the substrate, a gate electrode extending in a second direction surrounding the first and second active patterns, and a high dielectric film between the first and second active patterns and the gate electrode. The gate electrode includes first and second work function adjusting films surrounding the high dielectric film on the first and second active patterns, and a filling conductive film surrounding the first and second work function adjusting films. The first and second work function adjusting films include first and second work function conductive films, each of which includes a first metal film. A thickness of the first metal film of the first work function conductive film is greater than that of the second work function conductive film.

公开(公告)号：US20220415906A1

公开(公告)日：2022-12-29

申请号：US17577120

申请日：2022-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Il Park ,  Jae Hyun Park ,  Min Gyu Kim ,  Do Young Choi ,  Dae Won Ha

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor memory device and a method for manufacturing the same. The semiconductor memory device may include a substrate, a first lower wire pattern and a first upper wire pattern stacked on the substrate, and spaced apart from each other; a second lower wire pattern and a second upper wire pattern stacked on the substrate, spaced apart from each other, and spaced apart from the first lower and upper wire patterns; a first gate line surrounding the first lower wire pattern and the first upper wire pattern; a second gate line surrounding the second lower wire pattern and the second upper wire pattern and spaced apart from the first gate line; a first lower source/drain area; a first upper source/drain area; and a first overlapping contact that electrically connects the first lower source/drain area, the first upper source/drain area and the second gate line to each other.

公开(公告)号：US12243754B2

公开(公告)日：2025-03-04

申请号：US17517304

申请日：2021-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Young Choi ,  Sung Min Kim ,  Cheol Kim ,  Hyo Jin Kim ,  Dae Won Ha ,  Dong Woo Han

IPC: H01L21/3213 ,  H01L21/308 ,  H01L27/088 ,  H01L27/092

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.

公开(公告)号：US20230326971A1

公开(公告)日：2023-10-12

申请号：US18149398

申请日：2023-01-03

Applicant: Samsung Electronics Co.,Ltd.

Inventor： Kyu Man HWANG ,  Sung ll Park ,  Jae Hyun Park ,  Do Young Choi

IPC: H01L29/10 ,  H01L29/78

CPC classification number: H01L29/1033 ,  H01L29/7851

Abstract: A semiconductor device including a lower pattern extending in a first direction, a gate electrode on the lower pattern and extending in a second direction, a lower channel pattern on the lower pattern and comprising at least one lower sheet pattern, an upper channel pattern on the lower channel pattern and comprising at least one upper sheet pattern, wherein the upper channel pattern is spaced apart from the lower channel pattern in a third direction, the gate electrode comprises a lower gate electrode through which the lower sheet pattern passes and an upper gate electrode through which the upper sheet pattern passes, the lower gate electrode comprises a lower conductive liner layer defining a trench and a lower filling layer filling the trench, and an entire bottom surface of the upper gate electrode is higher than an upper surface of the lower gate electrode, may be provided.

公开(公告)号：US20220399330A1

公开(公告)日：2022-12-15

申请号：US17571954

申请日：2022-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung In Choi ,  Do Young Choi ,  Dong Myoung Kim ,  Jin Bum Kim ,  Hae Jun Yu

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern. A second gate insulating film is wrapped around each of the plurality of wire patterns.