知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.123 seconds)

    CLOCK SIGNAL GENERATOR AND OPERATING METHOD THEREOF
    1.
    发明公开
    CLOCK SIGNAL GENERATOR AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240267034A1

    公开(公告)日：2024-08-08

    申请号：US18416527

    申请日：2024-01-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jihyun Park ,  Bilal Ahmad Janjua ,  Chiweon Yoon ,  Jungyu Lee

    IPC: H03K3/011 ,  G05F1/46 ,  G05F3/26 ,  H03K3/0233

    CPC classification number: H03K3/011 ,  G05F1/468 ,  G05F3/262 ,  H03K3/0233

    Abstract: A method of generating clock signals includes: receiving a bandgap reference voltage from a bandgap reference circuit; generating a first current having a first curvature characteristic based on the bandgap reference voltage; generating a second current having a second curvature characteristic based on the bandgap reference voltage; generating a first complementary to absolute temperature (CTAT) current by adding the first current to the second current; receiving a temperature-variable voltage and a temperature-fixed voltage from a voltage generator; generating an offset current based on the temperature-variable voltage and the temperature-fixed voltage; generating a reference current by adding the first CTAT current to the offset current; and generating the clock signals by alternately discharging a first capacitor and a second capacitor based on the reference current, and charging the first capacitor and the second capacitor based on a power voltage.

    Resistive memory device
    2.
    发明授权
    Resistive memory device 有权

    公开(公告)号：US12029048B2

    公开(公告)日：2024-07-02

    申请号：US17526262

    申请日：2021-11-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunmog Park ,  Jungyu Lee ,  Daehwan Kang ,  Sungho Eun

    IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00

    CPC classification number: H10B63/84 ,  G11C13/0023 ,  H10N70/011 ,  H10N70/882

    Abstract: A resistive memory device includes: memory cells overlapping one another in a vertical direction within a cell array region and each including a switching element and a variable resistive element; first conductive lines each being connected to the switching element; a second conductive line connected to the variable resistive element and conductive pads arranged in a connection region and connected to respective one ends of the first conductive lines, respectively, and having different lengths in the second horizontal direction. A lower conductive pad from among the conductive pads includes a first portion covered by an upper conductive pad, and a second portion not covered by the upper conductive pad, and a thickness of each of the first and second portions in the vertical direction is greater than a thickness of each of the first conductive lines in the vertical direction.

    Memory device and operating method thereof
    3.
    发明授权
    Memory device and operating method thereof 有权

    公开(公告)号：US11615841B2

    公开(公告)日：2023-03-28

    申请号：US16871481

    申请日：2020-05-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Bilal Ahmad Janjua ,  Jongryul Kim ,  Venkataramana Gangasani ,  Jungyu Lee

    IPC: G11C16/10 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: A memory device includes a plurality of memory cells, each including a switching device and an information storage device connected to the switching device and having a phase change material, the plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a decoder circuit determining at least one of the plurality of memory cells to be a selected memory cell, and a program circuit configured to input a programming current to the selected memory cell to perform a programming operation and configured to detect a resistance of the selected memory cell to adjust a magnitude of the programming current.

    MEMORY DEVICE AND OPERATING METHOD THEREOF
    4.
    发明申请
    MEMORY DEVICE AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20210118502A1

    公开(公告)日：2021-04-22

    申请号：US16871481

    申请日：2020-05-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Bilal Ahmad Janjua ,  Jongryul Kim ,  Venkataramana Gangasani ,  Jungyu Lee

    IPC: G11C13/00

    Abstract: A memory device includes a plurality of memory cells, each including a switching device and an information storage device connected to the switching device and having a phase change material, the plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a decoder circuit determining at least one of the plurality of memory cells to be a selected memory cell, and a program circuit configured to input a programming current to the selected memory cell to perform a programming operation and configured to detect a resistance of the selected memory cell to adjust a magnitude of the programming current.

    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A VARIABLE RESISTANCE MEMORY
    7.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A VARIABLE RESISTANCE MEMORY 有权

    公开(公告)号：US20220384524A1

    公开(公告)日：2022-12-01

    申请号：US17738366

    申请日：2022-05-06

    Applicant: SAMSUNG ELECTRONICS CO.,LTD.

    Inventor： Hyunmog Park ,  Jungyu Lee

    IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

    Abstract: A three-dimensional memory device includes: a plurality of word line groups including a plurality of word lines; a plurality of bit line groups extending in a vertical direction and including a plurality of bit lines spaced apart from the plurality of word lines; a plurality of memory cells arranged between the plurality of word lines and the plurality of bit lines and including a switching component and a variable resistance memory component; a plurality of global bit line groups connected to the plurality of bit line groups, wherein each of the plurality of global bit line groups includes a plurality of global bit lines electrically connected to a plurality of bit lines included in one bit line group, respectively; and a pad structure including a plurality of connection units and a plurality of pad layers, wherein the plurality of connection units are connected to the plurality of word line groups.

    Resistive memory devices and methods of operating resistive memory devices
    8.
    发明授权
    Resistive memory devices and methods of operating resistive memory devices 有权

    公开(公告)号：US11120872B2

    公开(公告)日：2021-09-14

    申请号：US16848149

    申请日：2020-04-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungyu Lee ,  Bilal Ahmad Janjua

    IPC: G11C11/00 ,  G11C13/00

    Abstract: A resistive memory device includes a memory cell array of resistive memory cells connected to word and bit lines, each bay of the memory cell array including K tiles; a write/read circuit connected to the memory cell array through a row decoder and a column decoder, the write/read circuit being configured to perform a write operation in a target tile of the memory cell array, the write/read circuit comprising write drivers corresponding to the bays; a control voltage generator configured to generate first and second control voltages based on a reference current; and a control circuit configured to control the write/read circuit and the control voltage generator. A first write driver that corresponds to a first bay of the bays is configured to provide the target tile with a write current corresponding to a physical position of a selected memory cell of the target tile in the memory cell array.

    MEMORY DEVICE AND OPERATING METHOD THEREOF
    9.
    发明公开
    MEMORY DEVICE AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240242743A1

    公开(公告)日：2024-07-18

    申请号：US18368907

    申请日：2023-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jihyun Park ,  Jungyu Lee ,  Yumin Kim ,  Chiweon Yoon ,  Eunchan Lee

    IPC: G11C7/04 ,  G11C7/08 ,  G11C7/10 ,  G11C7/14

    CPC classification number: G11C7/04 ,  G11C7/08 ,  G11C7/1063 ,  G11C7/14

    Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a voltage generator configured to output a first voltage that varies according to temperature of the memory device, a second voltage that is constant regardless of the temperature, and a first reference voltage applied to at least one line among the plurality of word lines and the plurality of bit lines, and a temperature compensation circuit configured to generate a compensation offset voltage based on the first voltage and the second voltage, and output a second reference voltage based on the first reference voltage and the compensation offset voltage.

Patent Agency Ranking