公开(公告)号：US10665592B2

公开(公告)日：2020-05-26

申请号：US16108786

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungwoo Song ,  Kwangmin Kim ,  Jun Ho Lee ,  Hyuckjin Kang ,  Yong Kwan Kim ,  Sangyeon Han ,  Seguen Park

IPC: H01L29/06 ,  H01L27/108 ,  H01L23/532 ,  H01L27/24 ,  H01L27/22

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

公开(公告)号：US10453796B2

公开(公告)日：2019-10-22

申请号：US15706655

申请日：2017-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungwoo Song ,  Ye-Ro Lee ,  Kwangtae Hwang ,  Kwangmin Kim ,  Yong Kwan Kim ,  Jiyoung Kim

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/532 ,  H01L27/02 ,  H01L23/522

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

公开(公告)号：US09691769B2

公开(公告)日：2017-06-27

申请号：US14810739

申请日：2015-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjun Kim ,  Keeshik Park ,  Jungwoo Song ,  Sang-Jun Lee ,  Donggyun Han ,  Jaerok Kahng

IPC: H01L21/02 ,  H01L21/00 ,  H01L27/108 ,  H01L27/11521

CPC classification number: H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/11521 ,  H01L27/228

Abstract: A memory device includes a substrate including active areas and isolation areas, trenches in the isolation areas, active patterns in the active areas, the active patterns protruding from the substrate, isolation layers filling the trenches, gate trenches crossing the active patterns and the isolation layers, and gate line stacks filling the gate trenches, a first width of the gate trench in the isolation layer being greater than a second width of the gate trench in the active pattern.

公开(公告)号：US11114440B2

公开(公告)日：2021-09-07

申请号：US16805066

申请日：2020-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungwoo Song ,  Kwangmin Kim ,  Jun Ho Lee ,  Hyuckjin Kang ,  Yong Kwan Kim ,  Sangyeon Han ,  Seguen Park

IPC: H01L21/768 ,  H01L27/108 ,  H01L29/06 ,  H01L23/532 ,  H01L27/24 ,  H01L27/22

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

公开(公告)号：US09362225B2

公开(公告)日：2016-06-07

申请号：US14598228

申请日：2015-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungwoo Song ,  Jaekyu Lee

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/423 ,  H01L27/108 ,  H01L27/11 ,  H01L27/10 ,  H01L27/105 ,  H01L27/22 ,  H01L45/00 ,  H01L27/24 ,  H01L27/02

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L29/4236 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are data storage devices and methods of manufacturing the same. The device may include a plurality of cell selection parts formed in a substrate, a plate conductive pattern covering the cell selection parts and electrically connected to first terminals of the cell selection parts, a plurality of through-pillars penetrating the plate conductive pattern and insulated from the plate conductive pattern, and a plurality of data storage parts directly connected to the plurality of through-pillars, respectively. The data storage parts may be electrically connected to second terminals of the cell selection parts, respectively.

公开(公告)号：US11837545B2

公开(公告)日：2023-12-05

申请号：US17399043

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungwoo Song ,  Ye-Ro Lee ,  Kwangtae Hwang ,  Kwangmin Kim ,  Yong Kwan Kim ,  Jiyoung Kim

IPC: H10B12/00 ,  H01L23/532 ,  H01L27/02 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L21/768 ,  H01L27/0207 ,  H10B12/033 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/5222

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

公开(公告)号：US11778807B2

公开(公告)日：2023-10-03

申请号：US17371452

申请日：2021-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungwoo Song ,  Kwangmin Kim ,  Jun Ho Lee ,  Hyuckjin Kang ,  Yong Kwan Kim ,  Sangyeon Han ,  Seguen Park

IPC: H01L29/06 ,  H10B12/00 ,  H01L23/532 ,  H10B61/00 ,  H10B63/00 ,  H10N59/00

CPC classification number: H10B12/30 ,  H01L23/5329 ,  H01L29/0649 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485 ,  H10B61/00 ,  H10B63/00 ,  H10N59/00

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

公开(公告)号：US09917161B2

公开(公告)日：2018-03-13

申请号：US15238721

申请日：2016-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungwoo Song ,  Jaekyu Lee ,  Jaerok Kahng ,  YongJun Kim

IPC: H01L27/108 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/22

CPC classification number: H01L29/408 ,  H01L27/10811 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10891 ,  H01L27/228 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device includes active pillars protruding from a semiconductor substrate and spaced apart from each other in a first direction and a second direction that is perpendicular to the first direction, a word line extending in the first direction between the active pillars, a drain region disposed in an upper portion of each of the active pillars, and a separation pattern provided between the word line and the drain region. A bottom surface of the separation pattern is disposed at a lower level than a bottom surface of the drain region.