公开(公告)号：US09691769B2

公开(公告)日：2017-06-27

申请号：US14810739

申请日：2015-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjun Kim ,  Keeshik Park ,  Jungwoo Song ,  Sang-Jun Lee ,  Donggyun Han ,  Jaerok Kahng

IPC: H01L21/02 ,  H01L21/00 ,  H01L27/108 ,  H01L27/11521

CPC classification number: H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/11521 ,  H01L27/228

Abstract: A memory device includes a substrate including active areas and isolation areas, trenches in the isolation areas, active patterns in the active areas, the active patterns protruding from the substrate, isolation layers filling the trenches, gate trenches crossing the active patterns and the isolation layers, and gate line stacks filling the gate trenches, a first width of the gate trench in the isolation layer being greater than a second width of the gate trench in the active pattern.