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公开(公告)号：US12175912B2
公开(公告)日：2024-12-24
申请号：US18456977
申请日：2023-08-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwangmin Kim , Daegun Kim , Yonghun Son
Abstract: A display apparatus is disclosed. The display apparatus comprises: a first display module having an infrared (IR) signal receiver and a first wired port and second wired port configured to be connected to local area network (LAN) cables; and a second display module having a third wired port and fourth wired port configured to be connected to LAN cables, wherein the first display module is configured to: transmit a received IR signal to the second display module via a first LAN cable connected to the second wired port and third wired port, based on the IR signal received via the IR signal reception unit being a signal for controlling the second display module, and transmit a received control signal to the second display module via a second LAN cable, based on the control signal being received, via the second LAN cable, from an external device connected via the first wired port, and the second display module is configured to transmit an IR signal or a control signal to a neighboring third display module via a third LAN cable connected to the fourth wired port, based on the IR signal or the control signal being received via the first LAN cable.
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公开(公告)号：US11114440B2
公开(公告)日：2021-09-07
申请号：US16805066
申请日：2020-02-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jungwoo Song , Kwangmin Kim , Jun Ho Lee , Hyuckjin Kang , Yong Kwan Kim , Sangyeon Han , Seguen Park
IPC: H01L21/768 , H01L27/108 , H01L29/06 , H01L23/532 , H01L27/24 , H01L27/22
Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.
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公开(公告)号：US10665592B2
公开(公告)日：2020-05-26
申请号：US16108786
申请日：2018-08-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jungwoo Song , Kwangmin Kim , Jun Ho Lee , Hyuckjin Kang , Yong Kwan Kim , Sangyeon Han , Seguen Park
IPC: H01L29/06 , H01L27/108 , H01L23/532 , H01L27/24 , H01L27/22
Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.
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公开(公告)号：US10453796B2
公开(公告)日：2019-10-22
申请号：US15706655
申请日：2017-09-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jungwoo Song , Ye-Ro Lee , Kwangtae Hwang , Kwangmin Kim , Yong Kwan Kim , Jiyoung Kim
IPC: H01L27/108 , H01L21/768 , H01L23/532 , H01L27/02 , H01L23/522
Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.
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公开(公告)号：US20190164975A1
公开(公告)日：2019-05-30
申请号：US16108786
申请日：2018-08-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JUNGWOO SONG , Kwangmin Kim , Jun Ho Lee , Hyuckjin Kang , Yong Kwan Kim , Sangyeon Han , Seguen Park
IPC: H01L27/108 , H01L23/532 , H01L29/06
Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.
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Patent Agency Ranking
公开(公告)号：US20180096947A1
公开(公告)日：2018-04-05
申请号：US15608747
申请日：2017-05-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： KISEOK LEE , Sooho Shin , Juik Lee , Jun Ho Lee , Kwangmin Kim , Ilyoung Moon , Jemin Park , Bumseok Seo , Chan-Sic Yoon , Hoin Lee
IPC: H01L23/544 , H01L27/108
CPC classification number: H01L23/544 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.
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公开(公告)号：US11837545B2
公开(公告)日：2023-12-05
申请号：US17399043
申请日：2021-08-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jungwoo Song , Ye-Ro Lee , Kwangtae Hwang , Kwangmin Kim , Yong Kwan Kim , Jiyoung Kim
IPC: H10B12/00 , H01L23/532 , H01L27/02 , H01L21/768 , H01L23/522
CPC classification number: H01L23/5329 , H01L21/768 , H01L27/0207 , H10B12/033 , H10B12/053 , H10B12/315 , H10B12/34 , H10B12/482 , H10B12/485 , H01L21/7682 , H01L21/76897 , H01L23/5222
Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.
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公开(公告)号：US10964292B2
公开(公告)日：2021-03-30
申请号：US16656146
申请日：2019-10-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangmin Kim
IPC: G09G5/14
Abstract: A display system, a display apparatus, and a method of operating the same are provided. The display system includes: a plurality of display apparatuses connected in series to each other, each display apparatus including: a display, a signal inputter/outputter configured to receive an image signal as a data packet from a preceding display apparatus, and transmit the image signal to a next display apparatus, and a processor configured to: process, for display on the display, an image based on the received image signal, and based on an abnormality in the image displayed on the display, control the signal inputter/outputter to transmit, to the preceding display apparatus, a request for a corrected image signal, of which a signal characteristic in the received image signal is modified.
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公开(公告)号：US10026694B2
公开(公告)日：2018-07-17
申请号：US15608747
申请日：2017-05-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kiseok Lee , Sooho Shin , Juik Lee , Jun Ho Lee , Kwangmin Kim , Ilyoung Moon , Jemin Park , Bumseok Seo , Chan-Sic Yoon , Hoin Lee
IPC: H01L23/544 , H01L27/108
Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.
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公开(公告)号：US11778807B2
公开(公告)日：2023-10-03
申请号：US17371452
申请日：2021-07-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jungwoo Song , Kwangmin Kim , Jun Ho Lee , Hyuckjin Kang , Yong Kwan Kim , Sangyeon Han , Seguen Park
CPC classification number: H10B12/30 , H01L23/5329 , H01L29/0649 , H10B12/315 , H10B12/482 , H10B12/485 , H10B61/00 , H10B63/00 , H10N59/00
Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.
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